Non-Volatile Memory Options in Portable Designs

Choosing the right NVM can dramatically impact both the power profile and the price of your portable design.

Craig Zajac, Product Marketing Manager, Embedded NVM Group, Virage Logic Corporation

The number of functions being demanded by consumers in portable devices is growing every day. Gone are the days when it was acceptable to have separate devices providing voice access, email and web access, music, video, and gaming. As the number of features and functions embedded into portable devices increases, so does the need for embedded non-volatile memory (NVM).

Today NVM is used for code storage, digital rights management (DRM), configuration settings, device / vendor IDs, and performance tracking to name a few. This article will address the various options available for system designers to include NVM in their portable designs, and will outline the key advantages and disadvantages of each technology option.

Available Options
There are a growing number of options to include NVM in portable designs. The key to effectively selecting the right NVM solution is to understand the basics about both the application requirements and the NVM capabilities.

The most common NVM options for portable devices are:

  • External EEPROM: stand-alone EEPROM IC available from a wide range of suppliers
  • Embedded Flash: multiple-time programmable (MTP) NVM requiring a custom process and provided by the foundry
  • Logic OTP: one-time programmable (OTP) NVM done in a standard logic CMOS process, either available through the foundry or through third party IP providers
  • Logic MTP / FTP: multiple-time programmable (MTP) and few-times programmable (FTP) NVM done in a standard logic CMOS process, typically provided by third party IP providers

Understanding the application requirements (target process node and use model) is critical to narrowing the NVM options. Each option has clear advantages and disadvantages. For example, external EEPROM has the broadest range of bit counts and is completely process agnostic, but carries the burden of requiring an additional chip. Embedded flash has high endurance and is capable of supporting up to 1M bit of NVM, but requires a customized process that is not available in advanced process nodes. Logic MTP and Logic FTP provide true multiple time programmability across a wide range of process nodes, but the available densities are usually limited to 16 kbits or less. Logic OTP can cover a wide range of bit counts and process nodes, but has limited flexibility because there is only one programming cycle allowed.

Understanding the Use Model

System designers with a clear understanding of the use model can quickly narrow the number of options. The two key dimensions of the use model are the total number of bits needed and the total number of write cycles required of the NVM. As shown in Figure 1, each technology option is optimized for a particular region in the use model space. Applications that fall into one of these areas will have a straightforward decision regarding which NVM to use, assuming that it also meets the process, power, and cost requirements of the system.

NVM choices
Figure 1: NVM choices vary with density and endurance requirements

One subtlety that is often overlooked in the use model analysis involves the total number of program cycles needed. For an application requiring the final data to be written only one time, it is critical to understand where the data needs to be programmed. Programming at wafer sort (typically for simple trim applications) most likely requires one program cycle. If the programming needs to be done post-packaging or in the final system (precision trimming, configuration settings, device / vendor IDs, etc.) there are additional programming cycles required in order to fully test the NVM.

Depending on the outgoing quality level requirements, it may be acceptable to forego any testing of the NVM and ship untested arrays to the field. For applications where the quality requirements are more stringent, system designers may consider migrating to an FTP based solution, that allows the NVM array to be 100% tested before shipment.

Depending on the flexibility of the end use model, some applications can benefit from a hybrid solution that includes multiple technologies. A common example is using a small amount of Logic MTP or FTP in combination with a larger block Logic OTP or ROM to create a high density solution with the ability for small amounts of in-field programmability without the added cost of a custom Flash process or an external component.

Power Comparisons

Comparing the power consumption of NVM solutions is critical to understanding the impact on the overall system power budget. In this comparison, each of the technologies was evaluated based on an 8 kbit NVM array (the largest bit count commonly available across all categories). Read power, write power, and standby power are all summarized in the table below. In most cases, the standby power is driven by the process leakage and not by the NVM. For the read and program power, the values are driven by the underlying technology and the architectural tradeoffs.

For external EEPROM, the high power consumption is based on two factors. First, by being an external IC, the interface power is significantly higher than an embedded solution. Second, commodity EEPROM ICs are typically built on a customized process from older geometries and require higher supply voltages (3.3V or 5V) that increase the overall power consumption of the device.

For embedded Flash, the higher current is directly related to the capability to support higher density memory arrays. Many of the target applications for high density MTP use the NVM for code storage, and one of the key requirements for code storage applications is fast access time. In order to achieve faster read and program access times, embedded Flash NVM blocks require additional current.

The Logic OTP solutions also target code storage applications, so they trade off faster access times for higher power consumption, but a number of Logic OTP technologies also rely on a high current programming operation to create physical changes to the silicon structure. Both traditional poly fuse technology and more recent oxide rupture antifuse technology require a high current to permanently change the properties of the underlying silicon to program the NVM.

For the Logic MTP and FTP solutions, the low power is driven by the fact that the available memory densities typically do not support code storage, so the access time requirement is not as stringent. This allows the Logic MTP and FTP NVM blocks to better optimize for power consumption at the expense of access time.


External EEPROM

Embedded Flash

Logic OTP

Logic MTP / FTP

Read Power

5.5 mW

2.5 mW

13 mW

0.7 mW

Write Power

16 mW

17 mW

13 mW

1.7 mW

Standby Power

27 µW

25 µW

15 µW

13 µW

Cost Comparisons

Second only to the power considerations in portable systems is the overall cost implication. There are three basic components to the total cost of ownership:

  • Silicon costs are the costs associated with the reduced net die per wafer by embedding NVM, the additional process costs, or the cost of acquiring an external component
  • Test costs are the costs based on additional production testing as a result of including NVM
  • Qualitative costs are the costs that are subjective and include long-term reliability costs, operational support costs, risk, etc.

Silicon costs are the easiest to estimate. For external EEPROM, it is simply the component cost. For all of the logic based solutions it is the added cost due to the extra silicon area. For embedded Flash, the silicon costs need to include both the added silicon area, as well as the process cost adder due to the custom Flash process.

Figure 2 illustrates the silicon cost comparison for the MTP solutions (external EEPROM, embedded Flash, and Logic MTP). For small bit counts (typically less than 16k bits), Logic MTP is the most cost effective. Between 16k bits and 128k bits of external EEPROM offers the best silicon cost solution, and over 128k bits of embedded Flash wins. There are a number of variables that can affect the exact crossover point for the different technologies (die size and wafer cost in particular), but the analysis has yielded similar results across a broad range of ICs and process nodes.

silicon cost of NVM
Figure 2: Silicon cost comparison for multi-time programmable NVM solutions

Test costs for external EEPROMs are zero, as the devices should come completely tested from the manufacturer. Logic OTP has limited test costs, primarily due to the limited test capabilities of the architecture. Without the ability to electrically test the memory array, the test capabilities are limited to the support circuitry (digital control, charge pumps, etc.). For embedded Flash, Logic MTP, and Logic FTP, 100% electrical testing is possible. The overall test time is governed by the availability of test modes and capabilities in the specific NVM block.

 The qualitative costs are by far the most difficult to analyze and will depend on each company’s application specific requirements. Examples of qualitative costs that need consideration are, the cost of supporting an extra component in the bill of materials for the system, the extra pins and board space required to support an external EEPROM, field failures resulting from an inability to test the NVM array, and lack of supply flexibility by being tied to a foundry-specific solution. In most cases, the qualitative cost analysis is used as a tie-breaker when two technology solutions are approximately equal.


Embedded NVM is widely available from a number of sources for use in portable designs. For each application need, there is at least one potential option, and choosing the right selection requires not only a thorough understanding of the actual end use model, but the relative merits of each technology option.

Virage Logic Corporation
Fremont, CA
(510) 360-8000

This article first appeared in the October/November, 2008 issue of Portable Design. Reprinted with permission.

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