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Tag Archives: SOC
Power monitoring system leverages “dark servers” to cut data center power consumption as much as 50%
The growing discussions of “dark silicon” in SOC design came to mind as I read this article on the Phys.Org Web site about an entirely different sort of development: the creation of a power monitoring system for data centers that … Continue reading
More on the Xilinx EPP: Three ways to communicate with on-chip peripherals
Last month I discussed the newly introduced Xilinx Extensible Processing Platform (EPP), which represents a new product line and a new venture for FPGA leader Xilinx. To briefly recap, devices in the EPP device family are essentially a high-end microcontroller … Continue reading
Laser Spike Annealing of Nickel in Nanometer CMOS ICs Cuts Leakage 10x
One of the sad facts of life for nanometer silicon has been the rise of leakage current as device geometries shrink. At 65nm, CMOS leakage currents roughly equal operating currents, making it virtually impossible to reduce overall operating current by … Continue reading
Posted in CMOS, Design, EDA, Green Design, Low-Power, SOC
Tagged CMOS, EDA, leakage, Low-Power, process_technology, SOC
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Green Chips in Newport Beach
Yesterday, I moderated a panel on green chip design in Newport Beach at the 7th International SOC Conference. Chances are you didn’t see or hear any of it because there were only 100 people at this conference in total. That’s … Continue reading
Give OTP a chance for low-power, on-chip storage
The on-chip memories that get most of the attention are read/write memories such as SRAM, DRAM, Flash, and MRAM (which I just covered in my previous blog entry). However, there’s a place for OTP (one-time programmable) memory on chip, so … Continue reading
