Tag Archives: Low-Power

Want a peek over the shoulders during a real low-power microcontroller debate? Must-read info for all designers of low-power, microcontroller-based systems!

Recently, I published a blog post on my EDA360 Insider blog about the ARM Cortex-M0 processor core and its expected influence on mixed-signal, low-power IC design. (See “What effect does the ARM Cortex-M0 core have on mixed-signal microcontroller design?”) As … Continue reading

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Jan Rabaey’s remarkable short course in Low-Power Design Essentials, Part 4

Note: This blog entry is the final installment of four covering Professor Jan Rabaey’s excellent short course in low power design given at the January, 2012 meeting of the Santa Clara Valley Chapter of the IEEE Solid State Circuits Society. … Continue reading

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Laser Spike Annealing of Nickel in Nanometer CMOS ICs Cuts Leakage 10x

One of the sad facts of life for nanometer silicon has been the rise of leakage current as device geometries shrink. At 65nm, CMOS leakage currents roughly equal operating currents, making it virtually impossible to reduce overall operating current by … Continue reading

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Green Chips in Newport Beach

Yesterday, I moderated a panel on green chip design in Newport Beach at the 7th International SOC Conference. Chances are you didn’t see or hear any of it because there were only 100 people at this conference in total. That’s … Continue reading

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System-level design provides maximum control over power

Yesterday morning at DAC, Mentor Graphics rolled out a system-design tool called Vista (I guess Microsoft isn’t using that name any more). Mentor’s Vista is based on the OSCI TML 2.0 transaction-level modeling standard, which Mentor has adopted as a … Continue reading

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