The knobs in question are all dryer timer knobs on the stacked washer/dryers in our condo. All three come from the same vendor—a major US appliance manufacturer with a long, venerable history. Three plastic knobs on two models of washer/dryer from this manufacturer have broken in the same way. The knob’s plastic stem splits from the applied torque when using the knob to set a drying cycle and the knob no longer grips the control shaft of the dryer timer. After the knob breaks, the dryer can’t be used unless you clamp a pair of pliers to the control shaft to turn it.

When the first dryer knob split after a few years of use, I chalked it up to chance. I repaired the knob with plastic tubing, a metal cable clamp, and epoxy. Then it broke again and I found out that these plastic dryer knobs cost $20 to $25 each. I grumbled as I purchased the replacement knob from an appliance parts distributor.

Eventually, we had to replace the entire washer/dryer and it’s really hard to find many stackable washer/dryer models that use just one 220Vac plug between the washer and dryer. If you stack a separate washer and dryer, you’ll need a 110Vac socket for the washer and a 220Vac socket for the electric dryer. If I want that route, I’d need to run another circuit from the breaker box. That’s not so easy to do in a condo.

So we replaced our old washer/dryer with a newer model from the same manufacturer. It arrived with a much beefier dryer knob, which was broken on arrival. You could see from the white strain marks on the knob that the stem’s plastic walls were just too thin to handle the stress.

We immediately ordered a replacement under warranty. Meanwhile, we used a Radio Shack audio knob with a set screw as a replacement, which worked, but not well. The set screw in the knob quickly loosened. It took two weeks for the new dryer knob to arrive. It lasted less than a week. Here’s a photo of the cracked knob.

Here’s a closeup of the cracked shaft of the dryer knob:

As you can see, the knob’s thin plastic walls have failed. The shaft has split. This was the same problem I’d had with the two other cracked dryer knobs.

I can hear you now. It’s this particular vendor you say, but I don’t think so. If you Google “broken dryer knob,” you will get more than three million hits. Think about the amount of plastic waste represented by those search results. Think about the consumer cost at $20 or $25 a pop. It takes $40 to $75 million (retail) to replace that many dryer knobs and that’s only the parts cost to the consumer. This is anything but green design.

Here’s one person’s amusing solution to the broken dryer knob (warning: strong language):

Unfortunately the timer shaft on my dryer is made from Nylon plastic, so taking the “redneck” approach used in the video, arc-welding a steel nail to the shaft as a quick-and-dirty knob replacement and indicator, isn’t feasible in my case.

I found a better idea from an Amazon.com review of a (different) replacement dryer knob during my Google search. The reviewer complained of the same problem I have: the knobs are poorly designed, the plastic is too thin and soft, and the knobs split from the torque needed to turn the dryer timer shaft.

Simply said, these knobs are designed to fail. The Amazon.com reviewer filled his knob with epoxy, so that’s what I did with mine. I filled mine with steel-impregnated J-B Weld epoxy and let it cure for a couple of days.

Here’s a photo of the repaired knob:

Don’t bother telling me it’s a sloppy job because I know it looks sloppy. I had to apply a second round of epoxy because deep air bubbles rose to the top after a few hours and I wanted to be sure to fill the voids with more epoxy. I also had to seal in the metal shaft insert. Besides, this is the back side of the knob. No one will know it’s a sloppy job if I don’t blog about it, right?

The Amazon reviewer said he’s gotten more than five years of service from his repaired knob. I’m hoping to see the same. So far, we’re at one week and have withstood the initial use tests.

Meanwhile, how about spending an extra nickel on your next design to ensure that you’re not creating a three-million-knob pile of plastic scrap? The earth will thank you.

[I had planned on revealing the identity of my washer/dryer vendor but I see from the Google search that the problem is endemic to the entire appliance industry, so what’s the point? They all appear to be equally guilty.]

Low-Power Design Essentials, Part 3

One path that chip and system designers are taking to cut overall power consumption is to use multi-processor and multi-core architectures. The easiest route to multicore design is to create repetitive on-chip copies of a general-purpose processor that can run a wide range of tasks. However, that’s not the right thing to do, said Professor Rabaey, because general-purpose processors—by their nature—are not optimized for any particular task and therefore perform less than optimally on any given task from both speed and power perspectives. Instead, heterogeneous multi-processor architectures match computational architecture with the task to be executed—which is a far more optimal design approach.

In fact, asymmetric multiprocessing (AMP) can be more than ten times more efficient than a symmetric multiprocessing (SMP) design approach. Reconfigurable processors, claimed Professor Rabaey, can deliver another 10x improvement. Hard-wired designs that replace processors with dedicated state machines can deliver yet another 10x improvement in power efficiency at the loss of all programmability.

Dynamic power consumption is a function of hardware activity. At design time, you can only guess about a processor’s activity because you very likely do not have code traces that tell you what each processor will be doing from one moment to the next. Even the best guess represents just a single optimization point that will be inherently suboptimal nearly all of the time or even all of the time. (It is, after all, just a guess.)

Better: You can engineer a system to optimize dynamically at run time based on task load, which will result in a system that’s optimal at many points within the system’s operational envelope. That’s where the concept of dynamic voltage and frequency scaling (DVFS) came from. A system with DVFS capabilities can scale down frequency when activity levels are lower. Because the system isn’t running at full speed, it can also operate at a lower voltage. The combined effect of lower frequency and lower operating voltage results in significant power savings.

Another early experiment in dynamic power control was the use of a body bias voltage to adjust the threshold voltages of an IC’s transistors. A higher threshold voltage reduces leakage but requires a higher operating voltage. A lower threshold voltage permits lower operating voltages and therefore lower operating power levels at the expense of transistor speed and leakage. As an added benefit, adjusting threshold voltages with the use of body bias allows you to manage manufacturing process variation. However, the utility of this technique proved to be short-lived and it has all but disappeared below the 65nm or 45nm process nodes. FinFETs, expected to appear at or below 20nm, have no threshold control.

A very successful approach to activity-based dynamic-power optimization is the use of clock gating. Initially, large blocks were gated because their activity needs were simple to deduce from the system architecture. When the block wasn’t in use, it was not clocked. Analytical EDA tools have now introduced fine-grained clock gating that can stop the clock to smaller and smaller portions of a block based on projected activity. The tools work well and there is no longer any excuse not to use this technique, said Professor Rabaey.

However, even with excellent control over clocking using fine-grained clock gating, there’s still leakage power to deal with. Transistors are not ideal switches and there are many leakage paths that waste power while doing no useful work. We have developed many approaches to dealing with leakage said Professor Rabaey: transistor stacking, power gating, body biasing, and supply voltage ramping (which has proved to be the most effective approach).

• Transistor stacking increases gate fan-in and some stacked-transistor patterns are better than others. Ultimately, this approach has proven to have limited effectiveness.
• Power gating disconnects a block from the power rails and this approach works beautifully in a perfect world. But the world isn’t perfect; transistors leak and exhibit some amount of power-consuming resistance when turned on; and big transistors used to switch power leak even more than the small ones used to implement logic. So there are definitely compromises with this approach.
• Dynamic body biasing changes transistor threshold according to activity, which in turn reduces leakage. However, this approach has proven less effective at more advanced process nodes, as mentioned above, and has largely fallen out of use.
• Supply voltage ramping is similar to power gating but the supply voltage control is usually somewhere off-chip—in a power regulator for example. You need to have a multiple programmable voltage sources but these types of voltage supplies are becoming more common because of the rise of DVFS design. If there are system-level issues with or a need for memory retention, the supply voltage for the affected block need not drop all the way to zero but can drop to a low voltage that retains memory contents but does not permit switching activity.

The idea of supply voltage ramping leads you to rethinking a chip’s entire power-distribution network. As an analogy, the mains power-distribution system in the US does not route 110Vac everywhere. Instead, high-voltage, low-current electricity is distributed and converted to 110V near points of use. In the same manner, it’s possible to distribute higher supply voltages across a chip and to locally regulate down to required voltages at points of use. “This is hard to do for a standard IC,” said Professor Rabaey, “You really need a 16-core chip.” (Note: This approach has become quite common in system-level design over the past 20 years with the advent of small, efficient dc/dc switching regulators.)

The above discussion led to Professor Rabaey’s low-power mantra: slow, simple, many, dedicated, adaptive.

• “Slow” is self-evident. The slower you go, the less power you’ll need.
• “Simple” means “avoid power-consuming overhead that does not contribute to getting the task done.”
• “Many” invokes concurrency, the way you reduce clock rate.
• “Dedicated” means that the hardware is fully optimized for one specific task.
• “Adaptive” is a way to optimize when you do not know exactly what needs to be done prior to run time.

These are most of the tricks we’ve learned to use up to this point and we’ve used all of them to reduce system and chip power consumption to the level we’re at. These techniques have proved fairly useful. Consider the amount of computing we now perform in a hand-held mobile phone handset. One such handset represents more computing power than contained in most mainframe computers prior to the mid 1960s, yet the amount of power consumed is roughly three Watts and not hundreds or millions of kilowatts. In reality, we have drastically reduced the amount of power needed to compute, but by now we’ve used all the tricks we currently know how to use. Some of these tricks, such as dynamic body bias don’t even work anymore.

Now what? Are there new tricks? We’ll cover those in Part 4.

Note: This blog entry is Part 3 of a series based on a comprehensive one-evening course in low-power design essentials that UC Berkeley EECS Professor Jan Rabaey presented to about 100 people attending a meeting of the Santa Clara Valley chapter of the IEEE Solid State Circuits Society.

You can find Part 1 here and Part 2 here.

Low-Power Design Essentials, Part 2

There are many levels within the design hierarchy that provide you with opportunities to reduce power consumption. From highest benefit to lowest, these levels are:

• System/Application
• Software
• Microarchitecture
• Logic/Register Transfer Level
• Circuit level
• Devices

Hopefully, you will notice that the circuit and device levels—the levels with the least amount of leverage on and the smallest knob for controlling power consumption—are the levels we’ve most heavily relied upon for cutting system power. You should stop and think about that for a minute. Why should this be? Why have we relied on the least effective tools for controlling power consumption?

It’s because of the immense, powerful capability of Moore’s Law and Dennard Scaling. With Moore’s Law seemingly unstoppable and producing a new IC process generation every 18 months to two years, Dennard Scaling ensured that each new IC process node delivered transistors that were twice as fast and consumed half the power of previous-generation transistors.

That is, until recently.

Dennard Scaling broke at or near the 90nm node. We no longer get 50% power reductions with each new IC process node. According to Tom Beckley, Senior VP of R&D for Custom IC and Signoff at Cadence, the 20nm node—the node now being readied for production volume—potentially provides upwards of 20% better performance (not 100%), and a 30% power savings (not 50%). (See “Scaling the 20nm peaks to look at the 14nm cliff, Part 1: Tom Beckley from Cadence maps the challenges of advanced node design at ISQED”.)

At the system/application level, you have algorithmic choices that massively affect power consumption at the system level. You also have control over the amount of concurrency. The trend towards the use of multiple processor cores running at moderate clock rates rather than one processor core running at an extreme clock rate that’s at the limit of a process technology is but one example of a contemporary trend towards concurrency. Additional examples of this trend include the sudden appearance of algorithm- or application-specific hardware engines such as multi-core graphics processing units (GPUs), hardware H.264 video decoders, and separate audio processors in SoC design.

At the Microarchitecture level, you have choices between executing algorithms in parallel versus taking a pipelined approach. You can also choose between general-purpose execution engines (CPUs) and application-specific engines such as the ones noted at the end of the previous paragraph.

Finally dropping down into the actual hardware-implementation level (Logic/RT), you can pick from a logic family (general-purpose versus low-power) and you can choose either full custom IC design or standard-cell design. At the circuit level, you control device sizing, power-supply voltages, and transistor thresholds. Finally, you can select the actual device substrate material—bulk silicon versus SOI for example.

Nothing comes for free, said Rabaey. Power, Performance, Cost—you must always pay for one with one or both of the others. We are quite used to designing in the power/performance/cost design space (the power/performance/area or PPA space for semiconductor design—area = cost to first approximation in IC design), but there’s an equally valid power/delay space we could be operating within.

In many markets, we’ve been pushing performance hard, feeling the need to go as fast as possible. Our marketing of electronic products, as it does for automobiles, frequently emphasizes and glorifies speed. Some applications still need to run as fast as possible. But fewer and fewer systems these days really need more speed. Many systems can tolerate more application latency and we can, if we wish, back off on the speed to save energy and we now, increasingly, finding ourselves in an energy-constrained world.

Operating in the power/delay design space, we can choose from two extremes:

• Go as fast as possible, shoot for minimum delay and pay dearly in power consumption
• Maximize performance for a given energy budget

If you want to optimize both power and performance, you will need to cross-optimize design at all six of the levels listed above. Here are Rabaey’s four concrete guidelines for “energy-inspired” design:

• For maximum performance, maximize concurrency. You pay for this concurrency with area and power.
• For a given performance level, choose an optimal amount of concurrency to minimize energy consumption.
• For a given energy-consumption level, use the least amount of concurrency that meets performance goals.
• For minimum energy consumption, pick a design with minimum overhead—direct mapping of function to architecture.

One thing to get very clear in your head: we have often implemented functions inefficiently because we were not paying attention to energy efficiency when these functions were designed, and once designed in legacy and inertia can keep these less-efficient functional designs in use for a long time.

Inefficiencies in function-block designs arise from:

• Over-dimensioning and over-design
• Building generality into a design where none is needed
• Inefficient design methodologies—using methodologies that do not even consider energy consumption
• Limited design time, forcing the selection of less-than-optimal designs
• The need for flexibility, re-use, and programmability to accommodate unknown future enhancements

Professor Rabaey then supplied some simple guidelines for improving computational energy efficiency:

• Match computation to architecture. Dedicated functional solutions are far more energy-efficient that are general-purpose solutions
• Preserve an algorithm’s locality. Don’t move data very far unless needed. In other words, keep data local in registers or closely bound RAM, not out in bulk SDRAM whenever possible.
• Exploit signal statistics. Correlated data contains fewer transitions than random data—that’s the concept behind a 1-bit audio D/A converter, for example. Most of the time, audio signals transition smoothly from one value to the immediately adjacent value.
• Use energy only when demanded. It seems like a simple idea, but first consider how much time a PC processor spends in a loop waiting for a user to hit a key or move a mouse. Then think about the amount of power wasted in that loop. For contemporary desktop PC processors, there are tens of amps flowing through that processer in leakage current alone, not to mention the millions of instructions executed in the millions of wait-loop iterations. There are countless examples of wait loops burning power and consuming energy while waiting for something to happen in all sorts of electronic system designs. PCs are not exceptional in this regard.

Since the 1971 introduction of the commercial microprocessor by Intel, hardware programmability and flexibility have been the name of the game. Microprocessors have transformed system design for a variety of excellent reasons. They have shortened time to market: many of today’s systems could not be implemented in any practical manner without programmable microprocessors. Microprocessors encourage a lot of hardware design reuse. Often, it’s possible to base an entire product family on one board design that employs different firmware sets for different product family members.

We’ve also become dependent on the microprocessor’s ability to permit field updates. Just last month, I uploaded a needed firmware update for my video camcorder. The camcorder design predated the invention of Class 10 SDHC memory cards, so I discovered that the camcorder was not able to recognize the newer Flash memory media when I purchased a 32Gbyte SDHC card. A firmware update cured the problem.

However, says Rabaey, all of this flexibility through programmability comes at a large efficiency cost. Dedicated hardware is more energy-efficient and provides better throughput and latency but the use of dedicated hardware is counter to the processor-centric design trend of the last 40 years.

So the trick is to find a way to combine the flexibility of processor-based, firmware-centric design with the efficiency of dedicated hardware. Rabaey says that you do this by selecting simple processors over complex ones where possible, choosing concurrency over clock frequency whenever possible, stepping back from a “completely flexible” design mindset and adopting a design approach that relies more on “somewhat dedicated”—thus more efficient—hardware, and considering novel architectural solutions such as some form of hardware reconfigurability.

Note: This blog entry is Part 2 of a series based on a comprehensive one-evening course in low-power design essentials that UC Berkeley EECS Professor Jan Rabaey presented to about 100 people attending a meeting of the Santa Clara Valley chapter of the IEEE Solid State Circuits Society. You can find Part 1 here.

• By providing new solutions to old problems (power tools, appliances)
• Opening up and enabling new analog applications (solar, battery-driven bicycles, and other energy-efficient devices)
• By opening whole new markets that put electronics in places electronic systems have never been (building, bridge, and structure sensors; food-quality monitoring; portable medical instrumentation)

Analog plays a large role in many parts of the typical system block diagram. In fact, thanks to what Dr. Menon called “sensorization,” analog permeates the typical system design as shown in the block diagram he used during his keynote talk:

I interviewed Dr. Menon after his keynote speech. With analog ICs’ rapid unit growth relative to other semiconductors, with analog’s push deeper into existing markets, and with the entry into new markets as a backdrop, I wanted to hear Dr. Menon’s views on analog design’s role in low-power design, because there certainly is one. A big one.

In response to my question on the low-power aspects of analog ICs and system design, Dr. Menon chose to first focus on power conditioning. Power conversion and power management ICs are two large chunks of TI’s analog product portfolio, he noted. “Wired and wireless power ‘care-abouts’ are different,” said Menon. In the world of wired power, there’s certainly a concern about power efficiency but there’s a bigger concern about delivering consistent power in a world where the 220V or 240V power mains can fluctuate by 100V or even 200V. Delivering consistent power under those extreme conditions is the realm of power conditioners and power controllers.

In the world of unwired power—which includes laptops, portable medical equipment and instrumentation, and an exploding world of sensors—designers are looking for very long operational life from a battery charge. In some situations, you can never recharge the batteries (think strain and structural-integrity sensors embedded in bridges), yet you want years of operation from that sensor because they are difficult to replace. Except for the laptop computers, almost all of the systems designed for this battery-powered arena are based on microcontrollers, so designers are looking for low-power microcontrollers—and all such microcontrollers are now mixed-signal devices with substantial analog content.

Menon was quick to emphasize one such microcontroller, the Wolverine, just introduced by TI slightly more than one month ago. The headline of the Wolverine press release pretty much says it all: “TI’s new ‘Wolverine’ microcontroller platform slashes power by 50 percent versus any other microcontroller in the industry.”

Architecturally, the Wolverine is part of TI’s very successful MSP430 16-bit microcontroller family. Some of the Wolverine’s key low-power aspects include a 360 nA real-time-clock mode and less than 100 μA/MHz active power consumption. Also significant is the Worlverine’s on-chip, non-volatile memory storage. It’s based on FRAM (ferroelectric RAM) rather than Flash memory. If I am reading the press release correctly, TI says that FRAM consumes 250x less energy per bit than Flash or EEPROM memory commonly found in other microcontrollers.

Certainly one of the reasons for this huge energy advantage is that FRAM has fast enough write cycles to allow it to replace on-chip SRAM as well as Flash memory or EEPROM. The FRAM is a unified on-chip memory in the Wolverine implementation of the MPS430 microcontroller architecture, which not only offers energy advantages but also considerably cleans up the programming challenge of dealing with multiple types of on-chip memory. The press release also mentions “precision peripherals” including internal power management and a 12-bit A/D converter that runs on a mere 75μA. The need for precision in analog IC process technology was one of the main themes in Dr. Menon’s ISQED keynote.

Other big “care-abouts” in the battery-powered world, continued Menon,  are battery-charging circuits and battery-management ICs that can efficiently convert battery power to multiple supply voltages. The ICs that perform these tasks are essential to the product’s overall power use. You need ultra-low-leakage IC process technology for such products. In addition, non-volatile memory such as the FRAM used in the Wolverine microcontroller is very useful here as well, concluded Menon.

Limbo lower now
Limbo lower now

(From “Limbo Rock” by Chubby Checker)

How low can you go? ARM has pushed further into small-processor territory—going whole hog after the 8-bit processor cores—with the newly announced ARM Cortex-M0+ processor core. This is still a 32-bit processor core with the same 56-instruction Thumb ISA implemented by the ARM Cortex-M0 processor core. However, ARM has tossed more hardware overboard to cut the transistor count and the power requirements relative to the ARM Cortex-M0 core. Most noticeable is a jump from the ARM Cortex-M0 processor core’s 3-stage pipeline to the ARM Cortex-M0+ core’s 2-stage pipeline.

As a result, the ARM Cortex-M0+ core draws even less power than the already low-powered ARM Cortex-M0. For example, in 180nm process technology, the ARM Cortex-M0 core draws 73µW/MHz while the ARM Cortex-M0+ core draws 52µW/MHz. That’s nearly 30% less power. In 40nm process technology, the ARM Cortex-M0 draws 4µW/MHz while the ARM Cortex-M0+ processor core draws 3µW/MHz. OK, so it’s only a single microwatt of difference in power, but it’s 25% less (as they say in Marketing). Meanwhile, ARM gets slightly more performance from the ARM Cortex-M0+ core with the reduction in pipeline stages: a CoreMark/MHz score of 1.77 versus 1.62 for the ARM Cortex-M0 core.

Even though tiny, ARM has enhanced the Cortex-M0+ with some notable features including an optional 8-region Memory Protection Unit, one non-maskable and as many as 32 physical interrupts, sleep modes (with an optional data-retention mode), an optional 32×32-bit hardware single-cycle multiplier, optional CoreSight JTAG and debug ports, and an optional Micro Trace Buffer.

Often, there’s an automatic assumption that 32-bit processors require a larger code footprint in memory than required for 8-bit processors. It’s a natural assumption but it’s not necessarily true. The ARM Cortex-M0+ employs the Thumb ISA, which consists largely of 16-bit instructions that specify 32-bit operations. Meanwhile, 8-bit processors often require two- and three-byte instructions to specify 8-bit operations. The ARM Cortex-M0+ page shows a worst-case example of a 16-bit multiplication operation that requires 30 instruction bytes for an unspecified 8-bit processor while the ARM Cortex-M0+ processor executes the same operation (actually, a full 32×32-bit multiply) using one 16-bit instruction. Of course, your mileage may vary.

Because of the tiny real-estate footprint and extremely low power consumption, the ARM Cortex-M0 processor core has already caught the attention of some microcontroller vendors shooting for the very low end including NXP, STMicroelectronics, and NuvoTon. It has also become a popular processor core for use as a firmware-programmable state-machine replacement in SoC designs because the processor itself consumes only 0.04mm² in 90nm process technology and less than 0.01mm² in 40nm process technology. That’s 100 ARM Cortex-M0+ processors per square millimeter at 40nm—not including memory. The ARM Cortex-M0+ processor core will likely prove even more attractive than the ARM Cortex-M0 core to these vendors and SoC designers because of the even lower power consumption, the improved performance, and the available enhancement options.

Freescale has already announced plans to bring out a new Kinetis L family of microcontrollers based on the ARM M0+ processor core. The company plans on demonstrating some aspect of the Kinetis L family at the Design West Conference in Silicon Valley followed by the unveiling of more details at the Freescale Technology Forum being held in San Antonio, Texas this June.

“Why is power important today?” That’s how Rabaey started his presentation. He answered his question this way:

“Power now plays a role in virtually every component” of the electronic ecosystem, which consists of an infrastructural core—the “cloud” built with a massive number of computer racks, servers, high-speed routers, storage systems, and cooling systems; multiple networks of mobile devices connected to the cloud through cellular, WiFi, and other wireless and wired networks; and then the extended ecosystem of all electrically powered devices, which Rabaey called the “sensor swarm.” There are millions of servers and other large systems in the cloud—a constantly growing number. There are already billions of mobile devices connected to the cloud, and there are or will be hundreds of billions or trillions of devices in the sensor swarm. Each of these ecosystem niches has very different needs with respect to power and energy.

The majority of all computation is headed to the cloud. Why? That’s where the largest and most concentrated energy is located. That’s where the cooling systems are located. That’s where there’s room for massive amounts of storage. Ultimately, said Rabaey, 99% of all computation will be performed in the cloud because our appetite for computation and storage is insatiable. We will feed that ferocious appetite mostly by growing the cloud and mobile devices will be our means of accessing information in the cloud.

The mobile device tier exists to put information into and to extract information from the cloud. We can already see that tier expanding rapidly with Smartphones and tablets currently taking the lead. No doubt we will invent more device types as we devise new ways to collect and interpret the information we’re storing in the cloud.

Rabaey foresees an immense sensor swarm. He believes that sensors will essentially become as numerous as grains of sand on the beach. They’ll be in our walls, on our bodies, and in our bodies. Eventually, there will be trillions of these sensors in the swarm, all reporting to the cloud, so that the entire ecosystem can become more aware of its physical surroundings and manage itself accordingly. A simple example: a room should be able to switch its lights off when there’s no one in the room.

Each of these three ecosystem tiers has different power and energy needs. In fact, power (used as a synonym for both power and energy from this point on in this blog entry) plays a critical role for each of the three ecosystem tiers and it’s one of the most compelling factors driving the design of devices and systems in each tier. Performance is still key, but power is equally important because if you cannot design a device or system to work within the available power envelope, then you will not get the desired performance.

Rabaey then turned to the central tier—the cloud. After one or two years, he said, the annual cost of running a data center is approximately equal to the cost of powering and cooling the center. In other words, once the capital equipment is in place, equipment maintenance and upgrades are a small fraction of ongoing the operating cost. The energy costs needed to run and cool the data center consume almost the entire annual operating budget of the center and those costs are large—millions of dollars per center.

Mobile phone handsets have a different sort of power constraint: about 3W. That’s about all you can get from today’s battery technology and about all you can dissipate in a person’s hand without burning the skin. Asbestos gloves are not likely to become “hot” fashion accessories.

As far as new, more advanced battery technology, Rabaey said “Battery’s Law is slow, way slower than Moore’s Law.” However, the market is not so patient as to put up with Battery’s Law. Performance requirements are always escalating so design engineers must scale component power consumption to get more performance and more function from the same amount of power.

We have started to turn to multicore designs to get more performance per Watt, said Rabaey, “but multicore platforms are only a partial answer.” The real opportunities, he said, will come from architectural innovations—they will come from a system perspective.

Let me repeat that, because it’s been said for 10 years and it’s not sinking in based on my own observations:

The real opportunities will come from a system perspective.

Why?

Because, as Rabaey next said, once you’ve tried all the circuit tricks in the book (and we have, as you’ll see), you have to ask yourself “What can I do next?”

The sensor swarm, I think, is where Rabaey’s real interest lies. Why? Because I’ve seen him give presentations about sensor networks for years. Rabaey called sensors “disappearing electronics.” They need to be very low in cost, very small, and they need to be self-contained from an energy perspective.

Now mobile devices also need to be self-contained, but we often recharge them or change their batteries. That will not work for the sensor swarm. “We can’t replace batteries in trillions of devices,” said Rabaey. In other words, Rabaey believes that these sensors must either carry all the energy they’ll ever need in the form of a battery that neither needs replacing or charging or these sensor systems must be able to harvest useful energy from their environment (light, heat, electromagnetic radiation, or vibration). Such systems must use mere microwatts of power. This is a very tall order for today’s designers.

After refining the definition of the three ecosystem tiers, Rabaey then differentiated the power and energy needs of the three tiers. Power is more important for high-performance systems in the cloud. The central issue is heat removal followed by the delivery of peak power and then energy cost. Portable systems are all about battery life while “zero-power” sensors have unique requirements for energy scavenging and storage.

Having set the stage by defining the three electronic ecosystem tiers, Rabaey then gave a review of existing low-power design techniques that focused on digital circuit power and energy consumption. Although circuit power and energy consumption consists of two parts (dynamic and static), designers were able to ignore static power consumption (leakage) during most of the CMOS age, which really started in the early 1980s. During this golden age, process lithography scaling was a win-win proposition because it delivered linear power scaling with improved circuit speed. Who couldn’t love that? In fact, we loved it so much, we gave other power-reduction design techniques either lip service or a lick and a prayer. Circuit scaling worked so well, who could ask for anything more?

That was the golden age and this is now.

As we continued to scale into the “deep submicron” and then nanometer regions, we also began to reduce the power supply voltages to further cut power consumption. Old-timers will remember a time when everything digital (well, nearly everything digital) ran from a 5V power supply rail. This supply voltage was a holdover from the bipolar TTL (transistor-transistor logic) days of the 1970s and 1980s and that power supply voltage level stayed with us for a very long time. (Note: Really old timers will remember that the earlier RTL (resistor-transistor logic, NOT “register transfer level”) integrated circuits ran on 3V or 3.6V, so 5V is not a magic supply voltage. It just seemed that way for more than two decades.)

Eventually, however, we needed to continue reducing power consumption and dropping the power supply voltage was a great, relatively pain-free way to cut power consumption levels. So we first dropped supply levels to 3.3V.

Wow! Instant power reduction of nearly 60%!

Then came 2.5V quickly followed by a sliding decline to supply rails near 1V. If you want, you can actually run digital nanometer CMOS circuitry at 400 or 500mV.

But there was a trap waiting at lower supply voltage levels and we’ve sprung it. As the power supply voltage starts to approach the threshold voltage of the digital transistors, transistors don’t switch as fast. Once we got to 90nm, CMOS circuits started to lose performance even though transistor sizes continued to shrink under the unblinking glare of Moore’s Law. We’d upheld Moore’s Law but we’d killed Dennard Scaling in the process.

Memo to circuit designers: loss of performance is unacceptable. It’s uncompetitive. It’s unthinkable.

So the circuit designers’ answer, of course, was to drop the transistor threshold voltage to give back some of the lost speed. The downside of this approach is that the transistors don’t turn off as fast. They stay on for longer and longer amounts of time. During that time, power flows through the partially on transistors. Nevertheless, we have taken this path with the result that leakage levels have risen to the point that just about half of the power consumed by a device is now static dissipation.

Leakage. In the words of the children’s song: “There’s a hole in the bucket dear Liza, dear Liza.”

And so scaling alone will no longer take us in the direction we want to go with respect to power consumption. Going forward from here, we will still need to use all of the circuit tricks we have developed during the golden age of CMOS but we will also need to do something—many things—more.

Fortunately, there’s a lot more we can do. I’ll discuss that topic in the next blog entry about Jan Rabaey’s remarkable short course in low-power design.

More value at lower cost. Doesn’t that seem like a good deal?

Here’s what Cassidy wrote that triggered this blog:

“Clay Christensen has an idea: Scare the hell out of yourselves.

OK, that’s not precisely the way he put it. But the author of “The Innovator’s Dilemma” is all about new ideas. Not just new — but different, unorthodox, radical, uncertain, frightening and disruptive. You don’t solve old problems with old ideas. The other day, Christensen held a one-man teach-in for non-profits and their supporters at San Jose’s Mexican Heritage Plaza, preaching the gospel of “disruptive innovation.” It’s an idea that is embedded in Silicon Valley’s DNA. It is also an idea that is a lot easier to talk about than to actually deploy.”

So what’s the connection with “intelligent design”? I was immediately reminded of a great new product, a home thermostat of all things, that I’d just written up from last month’s CES show.(See “Friday Video: Two minutes of system-design expertise from Matt Rogers, VP of Engineering and founder of Nest and designer of the thermostat of the future”) The thermostat is from a new company called Nest and the product is called the Nest Learning Thermostat. It looks like an updated 21^st century version of the old golden Honeywell manual thermostats that were common in the 1950s and 1960s. (Noted industrial designer Henry Drefuss created the Honeywell thermostat’s iconic circular industrial design in 1952.)

However, unlike those old Honeywell thermostats that were based on bimetallic temperature-sensing coil springs and mercury tilt switches, the Nest Learning Thermostat is based on a 32-bit microprocessor. And a TCP/IP stack. And WiFi. In adding these specific technologies to its Learning Thermostat, Nest demonstrates a grasp of Christensen’s concept of the “Innovator’s Dilemma.”

How?

First, understand that the context of what we mean by “home” has changed. Frequently in the modern Western world, there’s no one home. That means the home’s heating and cooling requirements are different. Also, our definition of “home” increasingly includes a home WiFi network, possibly with access to the outside world through the home’s broadband router. Add some intelligence and connectivity to a thermostat, and you can disruptively change how we heat and cool our homes with a large resulting energy savings.

After installation, the Nest Learning Thermostat needs to know three things:

1. What’s your Zip code (Yes, I know there’s a US bias built in here. Early intelligence has its limits.)
2. Should the thermostat start to heat or cool your home?
3. What temperatures should the Nest Thermostat use to heat or cool your home while you are away?

After that, you set the thermostat to the desired current temperature and the Nest Learning Thermostat then starts to observe your daily habits (with respect to heating and cooling only!). It monitors when you turn up the heat (like in the morning) and when you turn it down (like before you go to sleep). It notes when you turn on the cooling (like when the afternoon sun starts to make it overly warm for you).

The Thermostat learns your daily routing and your weekend routine (weekend habits are different for most people) and by the eight day, the thermostat has developed a pretty good idea of your habits and strives to maintain a comfortable home for you by catering to those habits. The Nest Learning Thermostat can start to heat your home several minutes before you rise in the morning. (This is a major feature for those of us whose first job in the morning is to turn up the heat for our spouses so they can get up.)

You can log into your thermostat from your office to adjust the heat so that your home is warm by the time you return from work or to let the thermostat know you’re going out for dinner and the heat can be delayed for a few hours. And of course, you can do the same from your smartphone no matter where you are on the planet (assuming you’ve got cellular coverage wherever you are).

The Nest Learning Thermostat also tries to train you after it learns your habits. It wants you to learn better habits in terms of energy consumption. It does this by starting to display a small green leaf when you turn down the heat or taper off on the air conditioning relative to your habitual heating and cooling use. This leaf tells you that you’re saving energy and thus money. It’s a subtle form of coercion and some people won’t like being told what to do by a thermostat. Others—the ones most likely to buy this product—will appreciate the watchful eye.

None of this would be possible if the Nest Learning Thermostat did not have a 32-bit microprocessor and a WiFi connection. Note that it took an entirely new company to build a thermostat like this. Although Honeywell still makes thermostats, microprocessor-based ones at that, it’s not building anything like the Nest Learning Thermostat. At least not this year. We just had to replace the thermostat in our condo and it is a Honeywell thermostat. It’s a standard setback thermostat design with an LCD. I have to tell it the time. I have to program it for a setback sequence. And Honeywell knew that the user interface on this product was so unintuitive that it kindly included a fold-out instruction booklet that pokes out of the top left of the thermostat, as you can see from this photo.

Frankly, I find the display of the new Honeywell thermostat extremely confusing. It shows the current temperature on the left side in large characters, the setpoint temperature in somewhat smaller characters on the right side, and the time in even smaller characters in the middle. To me, it looks like the display information was simply thrown on the display with little consideration to how the information is portrayed. The time is not the central piece of information on a thermostat yet that information is central to the display, albeit in small characters. The two important and conjoined pieces of information, the current and setpoint temperatures, are spaced nearly as far apart on the display as possible. And there’s no fixing this design with a firmware update. That LCD’s permanently configured to save manufacturing cost.

Not, repeat not intelligent design.

You can bet that the Nest Intelligent Thermostat does not have an ungainly instruction booklet poking out of its sleek, smooth industrial design. To anyone who has ever used a regular dumb thermostat, the Nest Learning Thermostat’s everyday operational use appears to be entirely intuitive. And if you want to do more complex things with the Nest Learning Thermostat, you interact with it through a Web page, not a handful of multi-use rubber buttons and a limited (for cost reasons) LCD. For these reasons (and a few more), I think the Nest Learning Thermostat is one of the best examples of 21^st century intelligent design I’ve seen. It offers up several lessons in thoughtful design that I hope you will appreciate as much as I do.

Note: To read Mike Cassidy’s entire column, click on the following link: “Clay Christensen sees Silicon Valley non-profits’ dilemma as the innovator’s dilemma”

1. Fundamentals of low-power design and a review of well-established low-power design techniques
2. New low-power design techniques that will come into their own based on current technology and application trends.

This is a rare opportunity to get a concentrated presentation from Professor Jan Rabaey of UC Berkeley, who happens to be an excellent and engaging speaker. The short course will be taught at the TI Silicon Valley Auditorium (formerly National Semiconductor), 2900 Semiconductor Drive, Santa Clara, CA.

The charge is $50 plus a $3.74 event fee. Register here.

At least three major changes to NAND Flash technology in the recent past have caught my attention. The first such event I want to discuss in this blog entry is the HMC or Hybrid Memory Cube that Micron first announced last year and is now in joint development with major partners including Samsung and IBM.

I previously wrote about the HMC (see “3D Thursday: Hybrid Memory Cube—Does anyone know what’s happening with IBM and Micron?”) and its design is for high-performance computing systems that require extremely high throughput: 1 Tbit/sec. (See “Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?”) The HMC is a DRAM example of the kinds of memory modules we’re likely to see from the marriage of 3D IC assembly techniques and advanced NAND Flash devices.

The HMC runs many, many TSVs (through silicon vias) up through a stack of as many as four SDRAM die to access the inherent parallelism of the multiple DRAM arrays on each die. Each proprietary DRAM die in the HMC stack has 16 separate memory arrays, resulting in substantial potential parallelism and consequently, substantial potential memory throughput.

However, the high-performance approach of the HMC is not the only way to harness 3D assembly and semiconductor memory. For example, at the end of last year, I wrote an extended blog describing a thought experiment that employed the HMC design concepts using Wide I/O SDRAM instead of the special NAND Flash chips in the HMC. (See “3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?”) Wide I/O SDRAM presents four independent 128-bit DRAM channels to the host system, resulting in a high level of memory parallelism. Just not as high as for the HMC. In fact, the performance is about half that of the HMC but it’s still pretty good. The same parallelism concepts could be applied to NAND Flash devices designed to a similar Wide I/O specification for NAND Flash. The lower interface speeds enabled by a Wide I/O memory interface port really drop power consumption while maintaining good performance through the parallelism uncovered by the access to the multiple on-chip memory arrays.

I have not heard of any efforts to adopt the Wide I/O interface spec to NAND Flash devices. Not yet. But the move to extracting parallelism from the arrays on all memory chips is too attractive to ignore in a world that perpetually thirsts for bandwidth at low power.

At the end of the year, two other announcements directly related to NAND Flash memory have caught my eye: the introduction of the XQD memory card format and the ONFI 3.0 interface spec. The Compact Flash Association introduced the XQD memory card format in December 2011. The XQD memory card has a slightly larger footprint than an SD memory card and a somewhat smaller footprint than a Compact Flash (CF) memory card. It’s as thick as a CF card. But the really big difference here is the interface to the memory card. The XQD memory card uses a PCIe (PCI Express) interface clocked initially at 2.5 Gbits/sec, resulting in a maximum write speed of 125 Mbytes/sec.

That’s really fast and speed is important when you’re shooting large images at a fast rate, which occurs during HD video recording and at high burst speeds in high-resolution digital still cameras. Both such conditions exist in the new Nikon D4 DSLR, which Nikon launched just last week. The Nikon D4 DSLR can shoot 16.2 Mpixel frames at 10 to 11 frames per second. Normally, DSLRs use in-camera RAM to buffer burst-mode still captures but the Nikon D4 DSLR can accept the new XQD memory cards and Sony introduced the first series of such cards last week, concurrent with Nikon’s introduction of the Nikon D4 DSLR.

Sony claims that its H Series XQD card can accept bursts of 100 uncompressed still images from the Nikon D4 DSLR in continuous shot mode. That’s a huge jump in burst length for a digital still camera and will be invaluable in shooting images of sports activities, for example.

One of the secrets behind the XQD card format’s performance is that PCIe interface port, which is also unique in that it is a memory interface and is not derived from a disk interface. That should mean that a host processor doesn’t need a disk controller to operate an XQD card. The card can be mapped to the host processor’s memory bus and the controller can reside in each memory card. Eliminating the disk controller from the serial chain between the processor and the Flash memory chips should cut costs, reduce power consumption, and boost performance.

All of those benefits are welcome in the world of low-power design. After all, do we really need controllers controlling controllers in an efficient system design? I don’t think so.

Now before you bemoan the need of a controller in each memory card, you should be aware that there already is a controller in each CF and SD memory card. You don’t think that NAND Flash arrays already look like disk drives, do you? We do indeed currently have controllers controlling controllers in existing NAND Flash memory subsystems.

A PCIe interface spec should simplify things somewhat.

The third development that’s caught my eye in the Flash memory arena is the announcement of the ONFI 3.0 interface specification for Flash memory. The ONFI (Open NAND Flash Interface) Working Group introduced the third major revision of the ONFI spec nearly a year ago, in March 2011. What’s new is that there are now products appearing that use ONFI 3.0.

The advantage of the new ONFI specification is that it doubles transfer rates to 400 Mtransfers/sec using the NV-DDR2 200MHz double-data-rate (DDR) protocol while adopting 1.8V SSTL_18 signaling to cut the power dissipation of the interface. See a pattern evolving here? More performance and less power consumption. The question is whether or not ONFI 3.0 is real or not. Well, the memories now seem real because Intel and Micron jointly previewed a 128Gbit NAND Flash device in December with the derivative 64Gbit NAND Flash device going into production now. According to the joint Intel/Micron announcement, the 128Gbit device will be in volume production later this year after a “rapid transition” from the 64Gbit device.

However, an ONFI 3.0 memory device isn’t sufficient. You also need a controller on an SOC that can operate ONFI 3.0 devices. Cadence just introduced an ONFI 3.0 NAND Flash controller IP block and companion PHY IP today along with appropriate verification IP so it’s now possible to include an ONFI 3.0 NAND Flash controller in an SoC design using the standard ASIC flow.

As you can see, there’s a tremendous amount of new technological development going into NAND Flash memory and I see big things ahead this year, all to the benefit of low-power system designers.

28nm

Perhaps the biggest process innovation to hit the semiconductor industry, with a long-tail effect on low-power semiconductor design, will turn out to be the 28nm process node. Here are the clues on which I’m basing this opinion.

First, Xilinx provided a very long and detailed explanation as to why it selected the TSMC 28nm HPL process technology for all three members of its series 7 FPGAs (Virtex-7, Kintex-7, and Artex-7) over the TSMC 28nm HP and P process technologies. The 28nm HP process variant is strictly for high-performance designs and the 28nm LP process variant, which employs PolySiON (polysilicon/silicon oxy-nitride) gate oxide, delivers low leakage but also lower-performance transistors. The 28nm HPL process variant is a high-K metal-gate technology that produces high-speed, low-leakage transistors. (See “Xilinx 28nm low-power SoC design class, part 2: Process Technology”)

It’s not Xilinx’ selection of the 28nm HPL process that’s the highlight here—it’s the fact that there are two low-power variants of the 28nm process available to IC design teams. They have the flexibility to pick the process variant that best meets the objectives for a specific IC.

Altera took a different approach in developing a low-power FPGA based on 28nm process technology. Late last month, the company announced that it had started shipping low-power Arria V FPGAs based on the TSMC 28nm LP process variant because it allows the Arria V FPGA family to deliver “the lowest total power, lowest static power, and lowest transceiver power of any midrange FPGA family, consuming up to 40% less power compared to previous generation devices.”

It’s this flexibility in 28nm process variants that I think will allow all sorts of interesting low-power design techniques to be used in future products designed with 28nm process technology. And the 28nm process node is critically important for another reason: It appears to be the last process node to be manufactured without taking extraordinary measures in lithography. By that, I mean that after the 28nm node, we will be seeing a big bump in lithographic complexity, first through double, triple, and quadruple patterning and then through EUV (extreme ultraviolet, aka X-rays) lithography. Scaling is about to get much more difficult after 28nm.

3D IC Assembly 

Which leads me to the other big semiconductor manufacturing innovation whose time has apparently arrived: 3D IC assembly. I believe that the time has arrived for 3D IC assembly to become mainstream and that we will see a revolution in SoC design and development based on adding 3D design to the mix. There are just too many benefits to ignore and I discussed some of these in my previous blog post (Part A).

To recap, the big advantages are:

• A huge reduction in I/O power to transfer signals from chip to chip
• A huge increase in chip-to-chip bandwidth without increasing I/O power consumption or packaging costs
• Ability to intermix logic, memory, analog, and RF functions by implementing them on separately optimized die (using separately optimized process technologies) and then creating appropriate 3D assemblies
• Cost advantages by reducing average die size
• Reduction in pressure to jump to the next process node (and higher design and NRE costs) by providing an alternative path to SoC-level integration

These advantages cannot be ignored and indeed companies are not ignoring them. TSMC itself has already stepped in and proposed itself as a 1-stop shop for IC die manufacture and 3D assembly. (See “3D Week: The State of 3D IC assembly—December 2011”) Xilinx is already solidly in the 2.5D IC assembly camp with the Virtex-7 2000T FPGA and you can bet that technology will make its way down the product line as quickly as the costs of early adoption can be reduced.

JEDEC has announced the finalization of the Wide I/O SDRAM specification, which is essential to the development of 3D memory stacks with high-speed, low-power data-transfer features. (See “3D Week: JEDEC Wide I/O Memory spec cleared for use”

The economics of the entire industry now solidly point to the adoption of 3D IC assembly as a mainstream packaging technology. (See “3D Week: Driven by economics, it’s now one minute to 3D”) Between the increasing availability of 28nm process technology and the rise of 3D IC assembly, I see a new flowering of electronic design the likes of which we have not seen since the early 1990s, when surface-mount technology and ASIC design both came of age nearly simultaneously. That was truly an great era for the industry. The same sort of simultaneous advance in semiconductor and packaging technology is taking place with 28nm process technology and 3D IC assembly.

It’s a great time for low-power design.