Category Archives: SRAM

What is analog’s role in low-power design? Interview with TI’s VP of Analog Technology Development, Dr. Venu Menon

Last month, Dr. Venu Menon, VP of Analog Technology Development at Texas Instruments, gave a keynote speech at the ISQED conference in Silicon Valley titled “Applications Drive Analog Technology Development and Innovation.” During his keynote, Dr. Menon noted that analog … Continue reading

Posted in Analog, Design, Flash, FRAM, Low-Power, Microcontroller, SRAM | Tagged , , , | Leave a comment

Think Globally, Act in Parallel. What can you do with one million ARM cores acting in parallel and how do you get there?

Professor Steve Furber’s SpiNNaker project is in the news again. I wrote about Furber’s massively parallel brain-emulation project back on March 30 after listening to his keynote at this year’s DATE (Design Automation and Test Europe) conference in Grenoble, France. … Continue reading

Posted in ARM, CMOS, Design, DRAM, Low-Power, Networking, SDRAM, SOC, SRAM | Tagged , , , , , | Leave a comment

Need to cut IP power? (Who doesn’t?) “Press here” says Calypto

All SoCs are built with IP blocks. Some of those are legacy IP blocks. Some are purchased from other vendors. Some are developed in-house. All of them draw power—static and dynamic power. At nanometer lithographies, the way to cut static … Continue reading

Posted in Clock Gating, CMOS, Design, EDA, Low-Power, SRAM | Tagged , | Leave a comment