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Category Archives: SOC
Power monitoring system leverages “dark servers” to cut data center power consumption as much as 50%
The growing discussions of “dark silicon” in SOC design came to mind as I read this article on the Phys.Org Web site about an entirely different sort of development: the creation of a power monitoring system for data centers that … Continue reading
Jan Rabaey’s remarkable short course in Low-Power Design Essentials, Part 3
Note: This blog entry is the third of four covering Professor Jan Rabaey’s excellent short course in low power design given at the January, 2012 meeting of the Santa Clara Valley Chapter of the IEEE Solid State Circuits Society. Low-Power … Continue reading
Is 2012 going to be another breakout year for NAND Flash and Low-Power Design?
It’s just one week into the year, I am increasingly getting the feeling that 2012 is going to be a momentous, tumultuous year for semiconductor technology and low-power system design. Among the many recent events that are giving me this … Continue reading
2011: A great year for low-power design, wasn’t it?
2011 was a great year for low-power design. I don’t think I can remember a year as good to low-power designers. I thought I’d devote this blog to a review of some major developments in 2011 that made low-power designers’ … Continue reading
“Watt’s Next?” asks Chris Malachowsky, co-founder, NVIDIA Fellow, and Senior VP or Research
Everything—literally everything—we design today is defined by its power consumption said Chris Malachowsky, an NVIDIA co-founder, fellow, and senior VP of research. Malachowsky spoke yesterday at a luncheon during the ICCAD conference held this week in San Jose, California. At … Continue reading
Altera introduces SoC FPGA melding ARM Cortex-A9 dual-core processor complex with a 28nm FPGA fabric
Xilinx first started to talk publicly about the fusion of processors and FPGAs—a product now known as Zynq—in 2010 and has announced plans to roll out parts by the end of this year. It was inevitable that Altera would eventually … Continue reading
Think Globally, Act in Parallel. What can you do with one million ARM cores acting in parallel and how do you get there?
Professor Steve Furber’s SpiNNaker project is in the news again. I wrote about Furber’s massively parallel brain-emulation project back on March 30 after listening to his keynote at this year’s DATE (Design Automation and Test Europe) conference in Grenoble, France. … Continue reading
The DDR4 SDRAM spec and SoC design. What do we know now?
DDR4 SDRAM is coming. JEDEC may not have released the final spec yet but Samsung made the first DDR4 memory chip announcement in January of this year—a 2133MHz device built with a 30nm process technology—and Hynix followed suit in April … Continue reading
The incredible vanishing power of a machine instruction. Is this the way to the brain?
I attended DATE (Design and Test Europe) this month in Grenoble and was fascinated by Steve Furber’s keynote titled “Biologically-inspired massively-parallel architectures—computing beyond a million processors.” Furber’s introductory remarks really clarify what’s been happening to the energy cost per instruction … Continue reading
Posted in Design, Low-Power, Networking, SOC
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Xilinx Zynq EPPs create a new category that fits in among SoCs, FPGAs, and microcontrollers
After telegraphing its punch at ESC last spring, Xilinx has now introduced the first four members of its EPP product line and named them Zynq to differentiate them from the company’s FPGAs. (See “Xilinx redefines the high-end microcontroller with its … Continue reading
