Category Archives: Low-Power

Need to cut IP power? (Who doesn’t?) “Press here” says Calypto

All SoCs are built with IP blocks. Some of those are legacy IP blocks. Some are purchased from other vendors. Some are developed in-house. All of them draw power—static and dynamic power. At nanometer lithographies, the way to cut static … Continue reading

Posted in Clock Gating, CMOS, Design, EDA, Low-Power, SRAM | Tagged , | Leave a comment

The Return of Heathkit (in spirit) at Maker Faire

I visited the most recent edition of Maker Faire last month and from what I can see, the event just keeps rolling along. I think it’s exciting to be in the company of people who love to make things. Anything. … Continue reading

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The DDR4 SDRAM spec and SoC design. What do we know now?

DDR4 SDRAM is coming. JEDEC may not have released the final spec yet but Samsung made the first DDR4 memory chip announcement in January of this year—a 2133MHz device built with a 30nm process technology—and Hynix followed suit in April … Continue reading

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Sometimes, all you need is tape: 3M Uniformity Tape solves problem of uneven LED edge lighting

We’ve all seem LCD displays with LED backlights that provide non-uniform illumination. That’s one reason why fluorescent backlights have held on for as long as they have. It’s not like anyone enjoys designing in the high-voltage power supply for the … Continue reading

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Future cars: The word from GM at IDC’s Smart Technology World conference

Last month, IDC ran a really interesting conference called Smart Technology World. One unusual presentation was about energy use for transportation, given by Byron Shaw, Managing Director of Advanced Technology at General Motors of Silicon Valley. That’s right, GM has … Continue reading

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Going against the low-power grain to resurrect and improve a 31-year-old HP calculator

Monte J. Dalrymple is a man with a mission: take one of HP’s most celebrated calculators, the HP 41C, and bring it into the 21st century. He’s done this by reverse engineering the 30-year-old CMOS “Nut” processor designed into the … Continue reading

Posted in FPGA, Low-Power | Tagged , , | 2 Comments

Solar cell seller sold on California

There’s an interesting, well-written article on California’s and Silicon Valley’s suitability as a continuing base for high-tech companies and manufacturers published in today’s San Jose Mercury News. If you’ve been in high-tech for any length of time, you’ve repeatedly heard … Continue reading

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The incredible vanishing power of a machine instruction. Is this the way to the brain?

I attended DATE (Design and Test Europe) this month in Grenoble and was fascinated by Steve Furber’s keynote titled “Biologically-inspired massively-parallel architectures—computing beyond a million processors.” Furber’s introductory remarks really clarify what’s been happening to the energy cost per instruction … Continue reading

Posted in Design, Low-Power, Networking, SOC | 1 Comment

Xilinx Zynq EPPs create a new category that fits in among SoCs, FPGAs, and microcontrollers

After telegraphing its punch at ESC last spring, Xilinx has now introduced the first four members of its EPP product line and named them Zynq to differentiate them from the company’s FPGAs. (See “Xilinx redefines the high-end microcontroller with its … Continue reading

Posted in FPGA, IP, Low-Power, LPDDR, LPDDR2, SOC | 4 Comments

18th Annual Electronic Design Process Symposium brings together the top thinkers of the EDA world, April 7-8, Monterey, CA

EDPS (The Electronic Design Process Symposium) provides an exchange of ideas among the top thinkers, movers, and shakers who focus on how chips and systems are designed in the electronics industry. Attendees of this elite workshop have met each year … Continue reading

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