Steve Leibson

Give OTP a chance for low-power, on-chip storage

The on-chip memories that get most of the attention are read/write memories such as SRAM, DRAM, Flash, and MRAM (which I just covered in my previous blog entry). However, there’s a place for OTP (one-time programmable) memory on chip, so the technology bears some thought. I discussed OTP at last week’s GSA Emerging Opportunities Expo and Conference in Santa Clara, California with Jim Lipman of Sidense, a vendor that offers hard IP for on-chip OTP memory.

Sidense’s SiPROM memory cell consists of one specially designed FET as shown in the figure below. The special part of the FET’s design is a stepped gate-oxide layer with two thicknesses: thick and thin. Unprogrammed, the FET looks like a FET. Programming causes a controlled disruption in the thin part of the FET’s channel-oxide insulation to produce a conduction path from the FET’s gate to the conduction channel. Charge-coupled sense amps can detect whether or not an FET in the OTP array has or has not been programmed.

It’s because of the charge-coupled sense amps that Sidense’s SiPROM technology qualifies as a low-power memory technology. These sense amps are only on for tens of nanoseconds during a read cycle and are not powered continuously. This is a patented feature of Sidense’s technology.

Although designers have an obvious bias towards read/write technologies for on-chip memory, OTP memory can be quite useful for storing infrequently programmed or reprogrammed data such as calibration and trim settings, serial numbers, configurations, boot code, and security keys. This last application is particularly interesting. Lipman provided an example. The security keys for the HDMI digital display interface spec need about 2.5 kbits for storage. However, there’s the possibility that the security can be broken and that new keys will need to be distributed. A 16-kbit array of OTP memory can store about six sets of HDMI keys, which should be enough storage to last beyond the expected life of the end equipment.

You should also be aware of the factors that argue in favor of on-chip OTP memory. Sidense’s cells are about 1.2x larger than ROM cells, so there’s a 20% size penalty in exchange for the flexibility of programmability. In exchange for this size penalty, there’s no need for a mask change if the data stored in the OTP ROM needs to be changed in the factory or in the field (for an update).

In addition, Sidense’s OTP memory easily tracks IC manufacturing process changes although it’s hard IP, so Sidense must tailor the IP for each vendor’s process technology. Sidense’s SiPROM products are currently available from 180nm to 55nm and are portable to 40nm and below. Supported foundries include TSMC, UMC, Fujitsu Microelectronics, SMIC, Tower, IBM and Chartered.

It’s also interesting to compare OTP memory with Flash. Lipman says that Sidense’s OTP SiPROM cells are about half the size of Flash cells for a given semiconductor technology. In addition, the creation of Flash-cell floating gates adds process changes that can add roughly 30% to wafer production costs. Finally, Flash process technology is clearly getting into trouble as lithographies shrink. Some presenters at the recent Flash Memory Summit were predicting that the 22nm node might be the last node to support Flash memory, although such end-of-the-world prognostications from the semiconductor pundits are often wrong. By contrast, Sidense’s SiPROM cells require only standard CMOS processing, so the company claims it’s easier for their OTP memory than it is for Flash cells to track process improvements.

The Hubble Gets a Low-Power ASIC

As I watched Space Shuttle Atlantis pull away from a refurbished Hubble Space Telescope after a spectacular series of EVAs, I realized that it’s now time to look away from the spectacular in-orbit repair efforts of the astronaut/mission specialists and turn my attention to a bit of low-power high technology that went into Hubble during the repairs. Astronauts John Grunsfeld and Drew Feustel replaced four circuit boards in the Hubble’s disabled Advanced Camera for Surveys (ACS) with a new electronics module and an external low-voltage power supply. The existing 15V power supply, a dc-dc converter that had operated far beyond its MTBF rating, failed early in 2007. However, the ACS repair didn’t just replace the failed supply with a new external box; the astronauts also upgraded the ACS imaging system with a low-power ASIC.

Now ASICs are almost always designed for high-volume applications where the cost of the ASIC’s design can be amortized over a large number of chips. Almost always, but not always. In the case of the Hubble, the repair of the power supply required the replacement of the CEB (CCD Electronics Box), which includes the A/D conversion circuits for the ACS’ Wide-Field Channel (WFC) CCD imager. Markus Loose at Teledyne Scientific & Imaging realized that this repair was a prime opportunity for a low-power ASIC that he’d developed for other telescope imaging applications.

The ASIC is called SIDECAR (System for Image Digitization, Enhancement, Control And Retrieval). SIDECAR contains 36 analog digitizing channels for converting analog CCD signals into digital data streams. Each analog conversion channel on the SIDECAR ASIC consists of an analog preamp, a 16-bit/100KHz A/D converter, and a 12-bit/5MHz A/D converter. The AISC also contains a 16-bit, radiation-hardened microprocessor, memory, interfaces, digital I/O pins, and 20 DAC-driven analog output channels to bias the analog CCDs. Here’s a block diagram of the SIDECAR ASIC:

SIDECAR ASIC Block Diagram

And here’s what the SIDECAR ASIC looks like in its Hubble packaging:

SIDECAR ASIC used in Hubble upgrade

In low-power mode, the ASIC draws a mere 11 mW. Now low power is the omnipresent watchword for earthbound applications these days but it’s even more important for the SIDECAR ASIC’s intended platform—the infrared James Webb Space Telescope—where it will be used in the Webb’s Near Infrared Camera (NIRCam) and the Near Infrared Spectrograph (NIRSpec). A hot conversion chip radiating IR cannot be tolerated in applications where sensitive imagers are trying to resolve a few infrared photons from faint, distant stars. The SIDECAR ASIC will also be used in the Webb’s fine guidance sensors. It’s a versatile chip design; The hallmark of a good ASIC. It’s the low-power, low-weight, and space-saving aspects of SIDECAR that make the ASIC attractive for space applications, not its cost. NRE amortization doesn’t play a role here.

Although originally designed for the James Webb telescope, Teledyne’s SIDECAR ASIC has now found its way into the Hubble. In addition, four SIDECARs were installed in early 2007 into the imaging system of the University of Hawaii’s 2.2 meter telescope on Mauna Kea. Like all well-designed ASICs, the Teledyne SIDECAR seems to have established itself as the standard part for high-end scientific imaging applications. When it’s fully tuned up inside of Hubble, it’s possible that the SIDECAR ASIC will pull more and better images from the ACS’ Wide-Field Channel CCD with less noise. Let’s hope so.

Here are some links if you want to get much more detained info on the SIDECAR ASIC and the ACS Repair (ACS-R) mission:

Amazing Miniaturized ‘SIDECAR’ Drives Webb Telescope’s Signal

Updates on ACS-R, PowerPoint presentation by Marco Sirianni

Imaging Sensor Technologies for Astronomy, Planetary Exploration & Earth Observation, PowerPoint presentation by James Beletic

SIDECAR ASIC Product Brief