Steve Leibson

Ethernet ports, low power, and multimedia, Part 2

In the previous post, I discussed the huge potential power savings being enabled by the IEEE’s 802.1-az Ethernet specification now under development and early deployment. While IEEE 802.1-az promises to save significant amounts of power and energy through the use of sleep modes for inactive Ethernet ports, continuous stream-based multimedia applications of the various Ethernet standards cannot endure power-down and wake-up delays associated with the new specification. Consequently, the IEEE is also developing new standards to help Ethernet connections better handle these multimedia applications. But before discussing those new standards, it’s helpful to step back and take a look at the current state of multimedia networking because it closely resembles the networking situation with computers if you set your personal time machine to take you back in time by 30 years or so. (No DeLorean needed!)

Three decades ago, computer networking was in chaos. Each of the major mainframe and minicomputer vendors had a unique and mutually incompatible networking scheme. The electronics didn’t match. The bit rates didn’t match. The packetizing and de-packetizing schemes didn’t match. The error-detection and –correction schemes didn’t match. And just as important, the cables and connectors didn’t match. Any data center than supported hardware from multiple computer vendors needed a big box of cables with all sorts of connectors just to handle the incompatible networking schemes.

Chances are good that you have a similar box of cables at home to help you connect all of your multimedia devices together. I know I can connect one of my televisions with an RF coax cable, simple audio and video coax cables terminated with RCA plugs, RCA RGB component cables, or HDMI cables. My audio connections include simple RCA-plug audio cables, coaxial and optical TOSlink cables, and speaker wire without connectors. I do indeed have boxes full of AV cables that no longer match any of the AV components I now use. Worst of all, these are all dumb, dumb, dumb connections. The AV system components have no idea what’s coming over these cables. I need to configure each box (usually through a remote control I can’t find) to tell it which of the many back-panel ports to use for the audio and video signals and how the streamed information is encoded. For example, I need to manually tell my system which of the DVD audio streams to use while watching a video. You would think that reasonably good equipment would be able to detect and optimize the experience automatically, but my equipment can’t.

So it’s not much of a reach to envision a world where Ethernet-enabled AV equipment automagically discovers the abilities of the other equipment in a local AV network cloud and then collaborates with the other connected equipment to optimize each viewing or listening experience. That end is precisely the goal of the IEEE 802.1 AVB (audio video bridging) working groups. However, the goals go much farther than that. Imagine AV systems with multiple content sources and multiple listeners. Then imagine a network of AV components that can automatically optimize the listening and viewing experience for each AV network user simultaneously in real time. That scenario is also within the goals of the 802.1 AVB efforts. Part of the need is for components to discover the capabilities of other Ethernet-connected devices in the local AV component cloud. Part of the need is to reserve a substantial part of the cloud’s networking bandwidth for content streams that absolutely require low-latency, high-bandwidth content delivery.

This effort relies on three interwoven specifications:

• IEEE 802.1-AS – A timing synchronization standard
• IEEE 802.1-Qat – A stream-reservation protocol
• IEEE 802.1-Qav – A packet forwarding and queuing protocol that can accommodate isochronous and non-isochronous AV traffic using reserved bandwidth and regular data-type Ethernet traffic using best-effort packet delivery.

Together with the Energy Efficient Ethernet specification (802.1-az)  discussed in the previous blog entry (even AV components sleep sometimes), the IEEE 802.1 AVB specifications ensure even longer life for the Ethernet protocol, now going on its fourth decade of ever-widening deployment.

Ethernet ports, low power, and multimedia, Part 1

When you think about the massive affects that the Ethernet standards have had on system design, the overall impact is no less than staggering—and I do not use that term lightly. Thirty years ago, when Ethernet was new, networking was both provincial and fragmented. The only machines deemed worthy of “internetworking” were mainframes and minicomputers. The big-iron houses like IBM and the minicomputer vendors such as Digital Equipment Corp (DEC) and Hewlett-Packard all had proprietary networking standards. For example, IBM had SNA and DEC had DECnet. Then in 1980 the IEEE started a working group—802—to standardize a network based on the Ethernet protocols that Bob Metcalfe, David Boggs, Chuck Thacker, and Butler Lampson developed at Xerox PARC along the lines of Metcalfe’s PhD project (ALOHAnet). To see the original Ethernet hardware paraphernalia including its thick and unwieldy yellow coaxial backbone cable, its vampire-tap MAUs (media access units), and its special coaxial-cable coring tool, you might be excused for not predicting that Ethernet would take over the planet. But it did through ruthless evolution and continuous cost cutting, which reduced the cost of connection to less than a dollar. And as a result, every computer manufactured these days has either a wired or wireless Ethernet port or multiple ports of various Ethernet flavors.

The interoperability of today’s Ethernet-enabled devices is staggering. To see an iPad in a Starbucks coffee shop surfing Web servers in far-flung places such as Eastern Europe, India, Asia, or even North America through a casual WiFi connection is stunning—yet it is so commonplace that the feat rarely reaches our conscious minds these days. It just happens. Conjoined with that ease of connectivity however is a dark cloud: wasted energy to keep those billions of Ethernet connections alive even when they’re not carrying data. The energy numbers boggle the mind. In a recent Webinar, John Swanson from Synopsys listed a few jolting power-consumption figures. In the US alone, Ethernet ports attached to servers, network storage devices, routers, switches, and other networking equipment burn about 0.5 terawatts per year! Ethernet ports on computers, printers, edge switches, and other local devices installed in commercial, research, and educational institutions burn another 1.5 terawatts per year! Home-based ports burn about 2 terawatts per year! In all, that’s about 5 terawatts or $400 million worth of electricity per year just to keep the bits moving along all of the Ethernet ports in the US alone. And you know that all of those ports aren’t active all the time, yet most of them burn power 24/7. No wonder that the IEEE is now addressing the issue of wasted networking power through several new standards designed to make Ethernet use more efficient.

The key low-power standard under development is called the 802.1-az specification and it employs LLDPDU (link layer discovery protocol data units) to allow a switch and a device to negotiate sleep and quiet times when the Ethernet ports can actually be powered down. Implementations based on the 802.1-az specification will require new hardware and software but these new ports are backward compatible with the old, power-wasting kind of Ethernet port. If there’s no negotiation, there’s no sleep time and the ports will operate normally. However, when negotiation between two 802.1-az ports does take place, both ends of an Ethernet connection can time out and can power down their respective Ethernet MACs and PHYs, which will result in substantial power savings.

Currently, version D3.2 of the working group specification is circulating. More important perhaps, Ethernet controllers with 802.1-az port compatibility are already available as are some early PHY chips. The MAC part of the 802.1-az specification has not changed in a while according to Synopsys’ Swanson and only PHY changes are expected in the future.

Data applications for Ethernet can benefit greatly from the power reductions made possible by the 802.1-az specification but throughput- and latency-sensitive applications such as audio and video over Ethernet need additional support, which I’ll cover in the next blog post.

Multicore server, PC, and embedded designs push memory power, drive use of advanced DDR3 SDRAMs

Systems designers try all sorts of methods to reduce system power consumption. For years, we’ve relied on circuit tricks and have been reducing logic supply levels from the 5V power supplies that were so common in from the 1970s and throughout the 1980s to the 1V levels we now employ with today’s advanced logic chips. Memory supply voltages have dropped as well. For example, the original DDR SDRAMs had a 2.5V supply voltage and DDR2 SDDRAM employs 1.8V supply voltage. That’s nearly double today’s SOC, processor, and microcontroller core voltages. The reason for this lag in supply-voltage reduction is that memory vendors prefer to stay in the economic sweet spot for IC lithography as opposed to logic design which prefers to stay on or near the bleeding edge. Consequently, memory’s share of a system’s power-consumption pie has been rising and there really hasn’t been much attention paid to reducing memory power consumption. The advent of DDR3 SDRAM provides another opportunity to cut memory power through further reductions in memory supply voltage and coupled with advanced process technology, Samsung has attained a supply voltage of 1.35V for its 40nm DDR3 SDRAMs. This drop in memory supply voltage can produce a 38% cut in server power consumption, according to Samsung.

Performance isn’t really the engine that drives DDR3 adoption. The real driver is bandwidth and there are two design trends that force the quest for ever-increasing amounts of memory bandwidth. The first such design trend is the wholesale adoption of homogeneous and heterogeneous multicore architectures. As an industry, we’ve embraced the use of multiple processor cores as a solution to the death of Dennard scaling. Although most people attribute the increase in operating frequency and the decrease in per-transistor power consumption through lithographic shrinks to Moore’s Law, which Gordon Moore codified in an article he published in 1965 while working at Fairchild Semiconductor, that attribution is not factually correct. Moore simply predicted that the number of transistors on a chip would grow exponentially over time as lithographies shrank. It was IBM’s Robert Dennard who observed in 1974 that lithographic advances in IC manufacturing also consistently produced faster transistors that consumed less power. For decades, we’ve used Dennard scaling to produce faster and faster processors (while attributing the improvements to Moore’s Law).

The semiconductor industry has poured billions of dollars into keeping Moore’s Law alive but Dennard scaling died at 90nm. We continue to get more transistors on a chip with each advance in IC lithographic scaling, but the transistors no longer get appreciably faster, so the MHz wars have ended. Worse, pushing transistors to their performance limit now produces leaky transistors that dissipate as much power when off as when on. We now recognize that the way to get more performance is to use the transistor bounty to increase the number of processors and to distribute the work load across these processors without striving for multi-GHz clock rates.

With all of these on-chip processors executing code and accessing data on a multicore chip, system designers must find a way to make large amounts of inexpensive memory available to these processors. For the last decade, the most cost effective way to provide a system with large amounts of low-cost memory has been the SDRAM. The classic system design teams a multicore processor or SOC with one or more SDRAM channels. As memory bandwidth needs rise, the SDRAMs’ per-channel transfer rate and the number of SDRAM channels used has increased. DDR transfer rate have now reached and exceeded 1600 Mtransfers/sec and it’s not uncommon to find server processors with three SDRAM channels, for example. Because of the constant thirst for memory bandwidth, DDR3 SDRAM sales exceeded DDR2 SDRAM sales beginning with the first quarter of 2010, according to the leading SDRAM vendor Samsung, and the company expects DDR2’s share of SDRAM market sales to drop below 20% by the end of the year.

When you move that much data between a processor and memory, you’re likely to dissipate a considerable amount of power and indeed, memory power consumption has been on the rise. Lowering memory power consumption can substantially lower system-level power consumption. For example, states Samsung, going to 40nm, 2-Gbit DDR3 SDRAM with a 1.35V power supply can cut a server’s memory power consumption by 80% compared to the equivalent number of storage bits implemented with 60nm, 1-Gbit, DDR2 SDRAMs running at 1.8V and can even cut memory power consumption by 38% compared to equal-sized memory arrays consisting of 60nm, 1-Gbit, DDR2 SDRAMs running at 1.5V.

As a result, according to Samsung’s measurements, 40nm, 2-Gbit DDR3 SDRAMs running at 1.35V can cut power by an astonishing 38% at the system level for servers. To put that into economic perspective, says Samsung, the use of 1.35V DDR3 SDRAMs in a server can save 2564 kilowatt-hours per year. Samsung estimates that there will be 32 million servers operating in data centers worldwide by the end of this year. If they all were equipped with 1.35V DDR3 memory, the annual power consumption would be reduced by 82 terawatt-hours, worth an estimated $28 billion. That kind of money gets any data-center manager’s attention.

The same sort of energy savings apply to any multicore system whether it’s a server, a PC, or an embedded system based on a heterogeneous multicore processor design.

Laser Spike Annealing of Nickel in Nanometer CMOS ICs Cuts Leakage 10x

One of the sad facts of life for nanometer silicon has been the rise of leakage current as device geometries shrink. At 65nm, CMOS leakage currents roughly equal operating currents, making it virtually impossible to reduce overall operating current by more than half. I’ve long thought this was the result of low-V_t transistors that can never fully turn off, a consequence of the drive to recover speed that’s lost when supply voltages are cut to reduce operating power. Turns out there’s another culprit: nickel contamination that occurs when nickel atoms drift away from the nickel-silicide interface layer used to improve the connectivity of metal inter-layer contact plugs. The nickel atoms drift during the annealing process, which is used to drive the deposited nickel atoms into the transistors’ source and drain contact pads. The first of two annealing cycles drives the metallic nickel atoms into the silicon source and drain pads creating Ni₂Si silicide. A second, higher-temperature annealing process converts the Ni₂Si into NiSi, which has lower resistance and thus provides good electrical connectivity between the contact pad and the metal interconnect plug.

It turns out that the current “soak” annealing (which lasts for tens of seconds) processes allow the nickel atoms to drift far afield. Like beach sand in your bathing suit, the nickel gets into places you’d rather not have it. The drifting nickel atoms seem to have an affinity for silicon lattice discontinuities, which can be found at the outside ends of the transistor where source and drain diffusions meet the isolation trenches and in long, narrow voids that run from the source and drain regions towards and into the FET channel. Both of these hiding places cause leakage because the metallic nickel conducts electricity where there should be insulator or semiconductor material. Nickel at the ends of the transistor causes substrate leakage and nickel atoms in the channel naturally cause channel leakage.

Applied Materials and European semiconductor research powerhouse IMEC have jointly developed a laser-annealing process with one-millisecond duration instead of taking tens of seconds. As a result, the diffusing nickel doesn’t have time to drift into these unwanted places during the second annealing step that generates NiSi. Applied Materials described a similar laser-spike annealing process back in 2004 (see article here), but reportedly achieved only a 3-4% leakage reduction back then. This latest development appears to be a refinement of that earlier technique. The two companies will be presenting their findings at this week’s IEDM conference in Baltimore, Maryland.

IMEC and Applied Materials will indeed have pulled a rabbit out of the hat if this laser-spike annealing process plus the application of appropriate transistor-design rules result in cutting leakage currents by 90% for nanometer CMOS. Leakage-driven power loss has become a significant problem for advanced IC design and had appeared to be insurmountable, even with the addition of high-K and metal-gate processing. Now, it appears there’s a real solution with the best of all possible implications for system and logic designers: they don’t need to learn anything new. They can leave this fix to the design tools and to the process engineers and once again skirt the system-level and architectural issues of low-power design.

Green Chips in Newport Beach

Yesterday, I moderated a panel on green chip design in Newport Beach at the 7th International SOC Conference. Chances are you didn’t see or hear any of it because there were only 100 people at this conference in total. That’s really too bad because we had a great set of panelists:

1. Michel Laurence co-founded Octasic, which is a Montreal specialist in echo cancellation and has mastered the art of self-clocking or self-timed (asynchronous) logic design.
2. Jauher Zaidi, CEO, PalmChip Corporation, which was in the chip-design business but has now spun off those activities to focus more on SOC platform software.
3. Alan Ruberg, SPMT architect for SPMT, The Serial Port Memory Technology consortium, which is developing a high-performance, low-power, next-generation memory interface to replace the DDR families with an interface that uses fewer pins.
4. Dr. Simiack Haghighi, Principal Architect of Qualcomm’s CDMA Technology Architecture Group, which should need no introduction…and
5. Steve Carlson, VP of Product Marketing at Cadence (who kindly volunteered from the audience at the last minute when a panelist from another leading EDA company didn’t show).

I tossed out questions from readers of my blogs, some I developed on my own, and some that came from the panelists themselves. Here’s the first question and the panelists’ answers.

This was a cynical question from one of my blog readers: What’s the difference between the design of a Green Chip and one of those greyish Silicon ones?….More to my point – doesn’t Darwin take care of those companies who don’t design to a lower power solution than their competitors and, therefore, is this “Green Chip” thing just hopping aboard the Hype Bandwagon?

Cadence’s Steve Carlson quickly snagged this first question. His cool reply was that the industry’s focus on green technology has little to do with tree hugging. It’s all about business. The confluence of business issues such as cost and power and the social issues that draw the general press coverage, but business drives the design decisions.

Palmchip’s Jauher Zaidi agreed. There’s lots of hype about “green” these days, he said, but cost drives everything. Energy costs drive purchasing decisions at data centers, which use a lot of electrical power. Chip-design teams need power engineers now, he concluded.

SPMT’s Alan Ruberg also chimed in for this first question. Every Watt dissipated by a system requires another Watt in cooling, he said. So every Watt you save in a design delivers a 2-for-1 return in terms of energy savings. He added “By the year 2020, if trends continue on the present course, you’ll only be able to power 9% of a chip at any given time.”

How can that be? Why not just omit the other 91% of the design? Because all of the panelists can foresee a time in the rapidly approaching future when there will be specialized blocks for all the tasks performed by a chip, but not all tasks need be running simultaneously. For example, a mobile handset chip with functional blocks for a still camera and a video camera need power up only one of those blocks at a time because they share the lens and cannot operate simultaneously, yet they each require different optimizations so it makes sense to design special-purpose blocks (or get the relevant predesigned IP) for both functions and then power the one that’s needed.

There were some interesting independent observations that I noted in addition to the answers to the questions asked during the panel session:

Palmchip’s Jauher Zaidi noted that Amdahl’s Law applies to the power component of systems as well as to its usual application for analyzing execution time. It does no good to reduce the power of one system block by 10x in a system like the iPhone, for example, if it represents only a small part of the overall system power consumption. You end up reducing the system’s energy consumption very little. Power reduction requires a systemic approach.

Zaidi also noted that he needs to charge his iPhone three times a day and that he also manually turns functions on and off to extend battery life. He recommended that designers make it easier for users to manage their increasingly complex devices. I countered, saying that my kitchen doesn’t require such management. The microwave oven doesn’t turn itself on spontaneously and the refrigerator turns itself on and off automatically to maintain set temperatures. Surely we can manage more of the functions in today’s more intelligent systems in a… more intelligent manner. I submit that we’re better off trying to engineer smarter systems than smarter customers. Social engineers we’re not.

Cadence’s Steve Carlson estimated that less than one third of SOC designs today use DVFS (dynamic voltage and frequency scaling) and 10% or more don’t even use clock gating. Those are pretty dismal numbers in my opinion for practices that reduce an SOC’s power consumption and are known to work well.

Carlson noted that there’s lots of room for improvement.

Amen.

What would you ask my panelists about Green Chip design?

I’m chairing a panel on Green Chip design at the 7th International SOC Conference next week. What would you ask the panelists about green ASIC/FPGA design if you were there? Here’s a list of panelists:

“Green Chips: Technology, Trends, and Challenges in Low-Power Multicore SoC Designs” (http://j.mp/1D0hfW)

1. Dr. Barry Pangrle, Solutions Architect, Low Power, Design and Verification, Mentor Graphics.

2. Dr. Sho Long Chen, President, CEO, Founder and Chairman, Vweb Corporation

3. Michel Laurence co-founded Octasic.

4. Jasbinder Bhoot, Vice President, Worldwide Marketing, eASIC Corporation.

5. Jauher Zaidi, CEO, PalmChip Corporation

6. Alan Ruberg, SPMT architect for SPMT, The Serial Port Memory Technology consortium.