Category Archives: FPGA

Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W

Xilinx announced today that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, 36 … Continue reading

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Altera introduces SoC FPGA melding ARM Cortex-A9 dual-core processor complex with a 28nm FPGA fabric

Xilinx first started to talk publicly about the fusion of processors and FPGAs—a product now known as Zynq—in 2010 and has announced plans to roll out parts by the end of this year. It was inevitable that Altera would eventually … Continue reading

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Going against the low-power grain to resurrect and improve a 31-year-old HP calculator

Monte J. Dalrymple is a man with a mission: take one of HP’s most celebrated calculators, the HP 41C, and bring it into the 21st century. He’s done this by reverse engineering the 30-year-old CMOS “Nut” processor designed into the … Continue reading

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Xilinx Zynq EPPs create a new category that fits in among SoCs, FPGAs, and microcontrollers

After telegraphing its punch at ESC last spring, Xilinx has now introduced the first four members of its EPP product line and named them Zynq to differentiate them from the company’s FPGAs. (See “Xilinx redefines the high-end microcontroller with its … Continue reading

Posted in FPGA, IP, Low-Power, LPDDR, LPDDR2, SOC | 5 Comments

Low-Power Design with FPGAs: The Basics

Spiraling complexity in all facets of electronic design often cause us to take our eyes off the basics. A recent paper presented at the IEEE International Conference on Intelligent Control and Information Processing (ICICIP 2010), held in Dalian, China in … Continue reading

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More on the Xilinx EPP: Three ways to communicate with on-chip peripherals

Last month I discussed the newly introduced Xilinx Extensible Processing Platform (EPP), which represents a new product line and a new venture for FPGA leader Xilinx. To briefly recap, devices in the EPP device family are essentially a high-end microcontroller … Continue reading

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Xilinx redefines the high-end microcontroller with its ARM-based Extensible Processing Platform – Case Studies – Part 2

In my previous blog, I discussed the hard-core features of Xilinx’s new Extensible Processing Platform (EPP) and explained the device at the 50,000-foot level. In this blog, I’ll dig a bit deeper into the thinking behind the EPP’s FPGA fabric … Continue reading

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Xilinx redefines the high-end microcontroller with its ARM-based Extensible Processing Platform – Part 1

Last week at the Embedded Systems Conference (ESC) held in San Jose, California, Xilinx disclosed additional information about its upcoming Extensible Processing Platform (EPP), which I previously discussed in a February 1 blog entry written just after RTECC (the Real … Continue reading

Posted in Design, DRAM, FPGA, Low-Power, SOC | Tagged , , , | 2 Comments

Tabula FPGA Scatters Logic, Memory, and Power Across Space and Time

Here’s a head-scratcher for you. Why not create tesseract FPGAs? A tesseract is the 4-dimensional version of a 3D cube. (Just as a 3D cube can be unfolded to make a set of six connected 2D squares, a tesseract can … Continue reading

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Designing Low-Power Systems with FPGAs, Part 2

Literally within an hour of posting my last blog entry on designing low-power systems with FPGAs, Altera’s marketing engine issued a related email and dropped it into my inbox. Altera’s email pre-announces the company’s upcoming FPGAs based on 28nm lithography. … Continue reading

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