Steve Leibson

Intel releases low-power, 40Gbyte SSD for $125

Now it’s a trend. Last week, I wrote about the sub-$100, 2.5-inch, 32Gbyte SSD from OCZ. Now Intel makes low-cost SSDs a trend with the introduction of a $125 (when ordering 1000), 2.5-inch, 40Gbyte, “value” edition of its industry-leading X25 SSD, as reported by Computerworld’s Lucas Mearian. Intel’s new X25-V SSD employs a five-channel MLC NAND Flash controller and incorporates ten 4Gbyte MLC NAND flash chips resulting in sequential read and write speeds of 170MBytes/sec. and 35MBytes/sec, respectively. Compare that to the OCZ Onyx drives specs of 125Mbytes/sec and a write transfer rate of 75Mbytes/sec. However, it’s the power consumption that really differentiates these drives. Intel’s X25-V SSD dissipates 150mW (typical) in active mode and 75mW (typical) in idle mode compared to the OCZ Onyx drive’s power ratings of 1W active and 375mW idle. For embedded hardware designers paying close attention to every mW, that’s a huge difference. Intel’s X25-V SSD provides 25% more storage for about an eighth of the active power and about a quarter of the standby power.

OCZ’s 32Gbyte Onyx SSD breaks $100 barrier, cuts power

It was only a matter of time. Nobody doubts that solid-state disks (SSDs) will decline in price over time. The only questions are “How fast will prices fall?” and “How much storage will I get for my money”? PC component vendor OCZ contributed some answers to those questions yesterday by introducing a new low-cost line of “sub 100 dollar,” 32Gbyte, 2.5-inch, SATA II SSDs dubbed Onyx. The first in a planned series of low-cost SSDs, the 32Gbyte Onyx sports a read transfer rate of 125Mbytes/sec and a write transfer rate of 75Mbytes/sec. The Onyx drive is based on MLC (multi-level cell) NAND Flash devices, which might raise concerns about long-term reliability, but the drive sports an MTBF rating of 1.5 million hours and a 3-year warranty. As for power—the 32Gbyte Onyx drive consumes 1W while active and about a third of a Watt on standby. That’s roughly half the power required by a mechanical 2.5-inch HDD.

Designing Low-Power Systems with FPGAs

Actel has published a White Paper discussing low-power aspects of using FPGAs. It should not surprise you that the White Paper’s points and conclusions favor Actel’s Flash-based FPGAs over SRAM-based FPGAs from other vendors but that bias should not stop you from extracting some good meat from the document.

The first important point from the White Paper: designers considering the use of an FPGA have decided not to take the ASIC/SOC route for one of several reasons. Carefully tailored ASICs and SOCs should always deliver the lowest unit-cost system chip with the lowest power—but there’s always a cost. That cost involves a large and complex design process that requires a substantial team of trained silicon designers, a big stack of expensive ASIC design tools, expensive fabrication masks, and weeks or months of fabrication delay after tapeout. Contrast that with no up-front NRE costs for an FPGA, inexpensive FPGA design tools, and no need to be familiar with the arcane world of chip design when using an FPGA to implement a system. For system designs shipping in lower volumes, FPGAs are mighty attractive.

Once you decide to use an FPGA, you must then decide on the FPGA technology you’ll use (SRAM-based, Flash-based, or antifuse-based) and you must pick an FPGA vendor. Given that you’ve selected to take the FPGA route, there are five components of device power consumption for you to examine when evaluating different FPGA technologies:

• Static power (leakage)
• Dynamic power (frequency dependent)
• Power-up (or inrush power)
• Configuration power
• Sleep-mode power

The total energy consumed by the FPGA (which is the most important design criteria for battery-powered designs) combines all five of these power components over time. It’s here that the Actel White Paper unsurprisingly starts to make the case for Actel’s Flash-based FPGAs, but again, the information provided in the White Paper is instructional.

Figure 1 shows a startup scenario for SRAM-based and Flash-based FPGAs. Power is applied to the system at T0 (time = 0) on the graph. As the input power supply voltage rises from zero volts, the SRAM-based FPGA draws a large inrush current as its SRAM configuration array powers on. Is the inrush current really as large for an SRAM-based FPGA as shown in Figure 1? Is it as small for a Flash-based FPGA as shown in Figure 1? Well, there’s no scale (making Figure 1 a marketing graph), so who’s to say? What you should get from this point is that you need to find out what that inrush current is for the FPGA’s you’re considering.

Figure 1: FPGA power consumption for power-up stage

Something else of interest is happening in Figure 1 and you might be tempted to misinterpret it. The blue line representing the Flash-based FPGA power consumption starts to ramp up well before the purple line representing the SRAM-based FPGA. At first glance, the lines make it appear that the Flash-based FPGA will consume more power over time than the SRAM-based FPGA. However, what the curves actually show is that the SRAM-based FPGA needs time to download configuration data into its configuration SRAM while the Flash-based FPGA starts to perform its system duties more quickly because there’s no configuration overhead.

Figure 2, another marketing graph, compares the power consumption of an SRAM-based FPGA with that of a Flash-based FPGA. Keep in mind that this is a marketing graph comparing two unspecified FPGAs which may or may not have similar gate counts performing some sort of unspecified workload. However, what’s shown that is useful is that you do need to consider the FPGA’s power consumption in these various operating phases and you need to weight the power use by the amount of time your system will spend in each phase to arrive at an estimate for battery life.

Figure 2: FPGA power consumption in various operating stages

One final note of interest in the Actel White Paper is that a Flash-based FPGA configuration cell is smaller than an SRAM-based configuration cell, so leakage currents are also smaller for Flash-based FPGAs. This point appears in the “Static” sections of Figure 2.

Free White Paper on NAND Flash from Denali

NAND Flash manufacturing cost reductions of 60% per year sustained over nearly a decade have driven many technology changes, developments, compromises, and innovations. Prices have fallen even faster over the past five years, but the precipitous price decline could easily slow due to technical forces and in all likelihood, they will. Further, NAND Flash specifications are changing and will continue to change in predictable and unpredictable ways due to these forces. These changes will create new capabilities for NAND users, will impose extra performance burdens, and may ultimately limit the flexibility of NAND Flash in future device generations compared to what is available today.

This paper describes these trends in a series of warnings, enumerates the steps the semiconductor industry is taking to smooth product transition for NAND Flash users, and highlights developments that may create problems for NAND Flash users in the immediate future. NAND Flash trends discussed in this paper include:

• Page-size trends and their impact on NAND devices and controllers
• Changes to the spare area on NAND Flash devices
• Changing page architectures and ways to use the new architectures
• Increasing bit error rates and the associated rise in error correction code (ECC) complexity

NAND Flash manufacturers employ a broad variety of technology roadmaps, semiconductor implementation methodologies, and cost/performance optimization-and-tradeoff strategies to develop and manufacture NAND Flash devices. Diverse applications for NAND Flash memories drive similarly diverse performance specifications and requirements. “One Technology Roadmap Does Not Fit All” is an important guiding principle here. Consequently, products from some NAND Flash vendors may take somewhat different approaches to those described in this paper even though the vendors are responding to the same technical and market pressures considered below.

NAND-Flash controller designers may find the warnings and comments in this paper useful as they analyze important trends in NAND Flash management. In particular, advanced NAND Flash devices need extensive software management and error-correcting methodologies to create fully-functional memory subsystems that provide error-free data storage and they’ll need even more management and better ECC methodologies in the near future. From Denali. http://j.mp/tAjUo

Give OTP a chance for low-power, on-chip storage

The on-chip memories that get most of the attention are read/write memories such as SRAM, DRAM, Flash, and MRAM (which I just covered in my previous blog entry). However, there’s a place for OTP (one-time programmable) memory on chip, so the technology bears some thought. I discussed OTP at last week’s GSA Emerging Opportunities Expo and Conference in Santa Clara, California with Jim Lipman of Sidense, a vendor that offers hard IP for on-chip OTP memory.

Sidense’s SiPROM memory cell consists of one specially designed FET as shown in the figure below. The special part of the FET’s design is a stepped gate-oxide layer with two thicknesses: thick and thin. Unprogrammed, the FET looks like a FET. Programming causes a controlled disruption in the thin part of the FET’s channel-oxide insulation to produce a conduction path from the FET’s gate to the conduction channel. Charge-coupled sense amps can detect whether or not an FET in the OTP array has or has not been programmed.

It’s because of the charge-coupled sense amps that Sidense’s SiPROM technology qualifies as a low-power memory technology. These sense amps are only on for tens of nanoseconds during a read cycle and are not powered continuously. This is a patented feature of Sidense’s technology.

Although designers have an obvious bias towards read/write technologies for on-chip memory, OTP memory can be quite useful for storing infrequently programmed or reprogrammed data such as calibration and trim settings, serial numbers, configurations, boot code, and security keys. This last application is particularly interesting. Lipman provided an example. The security keys for the HDMI digital display interface spec need about 2.5 kbits for storage. However, there’s the possibility that the security can be broken and that new keys will need to be distributed. A 16-kbit array of OTP memory can store about six sets of HDMI keys, which should be enough storage to last beyond the expected life of the end equipment.

You should also be aware of the factors that argue in favor of on-chip OTP memory. Sidense’s cells are about 1.2x larger than ROM cells, so there’s a 20% size penalty in exchange for the flexibility of programmability. In exchange for this size penalty, there’s no need for a mask change if the data stored in the OTP ROM needs to be changed in the factory or in the field (for an update).

In addition, Sidense’s OTP memory easily tracks IC manufacturing process changes although it’s hard IP, so Sidense must tailor the IP for each vendor’s process technology. Sidense’s SiPROM products are currently available from 180nm to 55nm and are portable to 40nm and below. Supported foundries include TSMC, UMC, Fujitsu Microelectronics, SMIC, Tower, IBM and Chartered.

It’s also interesting to compare OTP memory with Flash. Lipman says that Sidense’s OTP SiPROM cells are about half the size of Flash cells for a given semiconductor technology. In addition, the creation of Flash-cell floating gates adds process changes that can add roughly 30% to wafer production costs. Finally, Flash process technology is clearly getting into trouble as lithographies shrink. Some presenters at the recent Flash Memory Summit were predicting that the 22nm node might be the last node to support Flash memory, although such end-of-the-world prognostications from the semiconductor pundits are often wrong. By contrast, Sidense’s SiPROM cells require only standard CMOS processing, so the company claims it’s easier for their OTP memory than it is for Flash cells to track process improvements.

Cut Power Through Peripheral Magic (and SSDs)

You might be focusing all your effort on developing low-power systems by concentrating your efforts on your system’s logic board. Did you stop to consider that you can also find a quick way to cut a lot of power consumption by re-evaluating your choice of peripherals? Here, I’m specifically writing about hard disk drives (HDDs). Many embedded systems, and larger systems, incorporate rotating, mechanical disk drives. Both IDE/PATA and SATA HDDs are increasingly common in all sorts of systems including many embedded designs. Your designs might use either type. I’ve just spent the last three days attending the Flash Memory Summit and the theme of the day and of the year was solid-state drives (SSDs)—assemblages of semiconductors that emulate HDDs at the interface level so that they can plug into existing interfaces in most systems. SSDs can replace HDDs in many cases and save you Watts of power.

Here’s where a bit of digression is in order. The HDD industry has hit bottom on cost, resulting in the $30 HDD, as explained at the Flash Memory Summit by Sun Microsystems’ Lead Technologist for Flash Memory, Michael Cornwell. The $30 HDD has one platter and one head. It’s the cheapest thing the HDD vendors can make. It rides the bit-density curve and whatever fits on one platter at any given time is what the capacity is. It costs $30 (hence the name).

Lots of embedded products use this cheap HDD for secondary storage. The $30 HDD’s capacity is presently 120 Gbytes, which conveniently works out to 25 cents per Gbyte of storage. However, HDD capacity never stands still. The industry has a consensus road map for improving HDD density 10-30x and the $30 HDD will ride that curve like all of the more expensive HDDs. They will still cost $30.

SSDs of equivalent capacity cost more than $30. A lot more. And they will for a while. While many industry pundits predicted a crossover in cost per Gbyte last year when NAND Flash prices were dropping like a rock, the picture is quite different this year. NAND Flash prices aren’t falling nearly so fast so the pundits are saying (this year) that SSDs will never reach price parity with equivalent-sized HDDs.

For a lot of products, that smaller drive capacity doesn’t matter. For many products, 120 Gbytes of capacity is already way too much and yet that’s the smallest HDD increment you can get today. Not so with SSDs, which are based on NAND Flash chips, not spinning platters. For example, you can get IDE/PATA and SATA SSDs from SanDisk in capacities from 8 to 64 Gbytes. If those capacities work for your design, then you’ll like the power consumption: 0.5W typical, 0.15W average (typical), and 15mW in sleep mode. If the smaller capacities work for your design, you can also save money because at least some of those SanDisk SSDs cost less than $30. Also note that an SSD wakes up much faster than an HDD, so a sleep mode spec has considerable value in many applications.

Switching from an HDD to an SSD may be a very easy way to carve out some power consumption from your design. As an added bonus, the SanDisk drives are even smaller than a conventional 1.8-inch HDD, so you can carve some cubic millimeters from your system design and you can save on BOM cost as well. SSDs have a lot to commend them and merit consideration in your design.

State-of-the-Art in Low-Power Memory: Denali’s MemCon

Need gobs of cheap RAM? Need it to operate at the lowest possible power? This blog’s for you.

I attended Denali’s ninth annual MemCon conference a few days ago. It was three days of intensive discussion about the state of the art in DRAM and Flash memory-the two mainstay memory technologies in use today. Surprisingly, NAND Flash memory is now the low-cost leader in terms of cost per bit, having passed by DRAM a few years ago. However, DRAM remains the mainstay memory for the vast number of designs and DDR SDRAM now rules as it becomes easier and easier to find microcontrollers and FPGAs with direct DDR interfaces and DDR controller and PHY IP for SOCs.

Memory power consumption as a percentage of system power consumption has grown with the rapid growth of memory-array size in all sorts of systems. A real eye opener at MemCon 09 was a chart on the power consumption of memory in server systems, where the large server memory arrays consume as much as 40% of the system power and the processor now consumes a mere 28%. Why is that important? It’s important because big server users like Google pay tens of millions of dollars each year in electrical power costs to run and to cool their server farms and 40% of a few tens of millions of dollars is, well, tens of millions of dollars.

Note that the current share-of-power percentages for servers don’t make processor power consumption unimportant-28% is still a big number-but the clear message is that server designers must now be far more concerned with memory power consumption because it’s a big part of the power puzzle. As embedded designs adopt large DDR memory DIMMs for bulk memory, the same sort of situation applies. Embedded designers must also be aware of the way their DRAM choices affect system power.

Marc Greenberg, Denali’s Director of Technical Marketing, gave a 2-hour tutorial on low-power DDR SDRAM on the first day of MemCon09. He threw up one slide that does a terrific job of putting all of the low-power SDRAM parts in perspective:

Low-Power DDR Selection Criteria

This slide shows the optimum type of SDRAM to use based on your design’s memory-capacity and speed requirements. I like this slide a lot because it helps you to pick from the wide array of DDR types and speeds. However, it seems that your selection job is about to become a lot simpler. Look what happens to the chart when you add in LPDDR2 memory:

Low-Power DDR Selection Criteria with LPDDR2

LPDDR2 memory delivers the low-power goods by operating the SDRAM’s memory core and I/O at 1.2V, which is what you need to do to substantially cut memory power these days. Several manufacturers have announced LPDDR parts with I/O speeds to 400MHz/DDR800 and spec sheets for these parts are beginning to appear on DRAM vendor Web sites. LPDDR2 vendors with announced parts include Elpida, Hynix, Micron, and Nanya. Note that there’s also the possibility for existing LPDDR1 vendors to create parts that operate at 1.2V for similar power savings and that some of the soon-to-be-seen DDR3 parts may operate at 1.35V, which qualify them as low-power DRAMS.

In addition, there’s a spec for LPDDR2 non-volatile memory (LPDDR2-NVM) to allow LPDDR2 DRAM and Flash to be intermixed. The big advantage of Flash LPDDR2 is the very low standby power but Flash memory exhibits both read and write wear-out failure, so DRAM isn’t yet obsolete and you’ll likely need both memory types in your system design. The LPDDR2-NVM spec allows for I/O speeds to 533MHz/DDR1066 operation, but Greenberg says that the initial LPDDR2-NVM parts are likely to be slower than the maximum.