Category Archives: EDA

Is 2012 going to be another breakout year for NAND Flash and Low-Power Design?

It’s just one week into the year, I am increasingly getting the feeling that 2012 is going to be a momentous, tumultuous year for semiconductor technology and low-power system design. Among the many recent events that are giving me this … Continue reading

Posted in EDA, Flash, SDRAM, SOC, Video | Tagged , , , , , , , | 4 Comments

Need to cut IP power? (Who doesn’t?) “Press here” says Calypto

All SoCs are built with IP blocks. Some of those are legacy IP blocks. Some are purchased from other vendors. Some are developed in-house. All of them draw power—static and dynamic power. At nanometer lithographies, the way to cut static … Continue reading

Posted in Clock Gating, CMOS, Design, EDA, Low-Power, SRAM | Tagged , | Leave a comment

18th Annual Electronic Design Process Symposium brings together the top thinkers of the EDA world, April 7-8, Monterey, CA

EDPS (The Electronic Design Process Symposium) provides an exchange of ideas among the top thinkers, movers, and shakers who focus on how chips and systems are designed in the electronics industry. Attendees of this elite workshop have met each year … Continue reading

Posted in Design, EDA, Low-Power, SOC | Leave a comment

More on Mentor’s Catapult C from John Cooley and Other Designers

Earlier this month, I wrote about Mentor’s C-to-gates synthesis tool Catapult C and low-power design. The EDA industry’s self-appointed gadfly and uber-user John Cooley has just written an extensive blog posting about Catapult C complete with detailed comments from several … Continue reading

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Laser Spike Annealing of Nickel in Nanometer CMOS ICs Cuts Leakage 10x

One of the sad facts of life for nanometer silicon has been the rise of leakage current as device geometries shrink. At 65nm, CMOS leakage currents roughly equal operating currents, making it virtually impossible to reduce overall operating current by … Continue reading

Posted in CMOS, Design, EDA, Green Design, Low-Power, SOC | Tagged , , , , , | Leave a comment

What do Superman, ASIC and SOC Design, and Newport Beach have in common?

Hi. Do you design ASICs or SOCs? Do you work on a team that designs ASICs or SOCs? Do you manage a team that designs ASICs or SOCs? Let me ask you a question then. What’s the one thing you … Continue reading

Posted in Design, EDA, ESL, Low-Power | Leave a comment

Drop-in Synopsys’ DesignWare minPower IP components and cut ASIC power

Last week, I listened to a Webinar by Synopsys’ Jay Chiang on the DesignWare minPower IP components that the company introduced at this year’s DAC. Chiang did an excellent job and made a compelling case for using these IP components. … Continue reading

Posted in EDA, Low-Power | Tagged , | Leave a comment

Could A Low-Power Middle Ground Between ASICs/SOCs and FPGAs Help You?

You can’t always get what you want, But if you try sometime, You’ll find, You get what you need. Those lyrics from a song from the Rolling Stones describes the situation with ASICs/SOCs and FPGAs. For low power, you want … Continue reading

Posted in CMOS, Design, EDA, Low-Power | Tagged , , , | 1 Comment

Squeezing Excess Power Out of Synthesized Blocks

With the glacial-like industry move towards transaction-level simulation using OSCI’s TLM 2.0, I think that C and SystemC will be used more and more for the initial descriptions of large portions of many systems. Many system blocks will therefore end … Continue reading

Posted in Design, EDA, Low-Power | 1 Comment

System-level design provides maximum control over power

Yesterday morning at DAC, Mentor Graphics rolled out a system-design tool called Vista (I guess Microsoft isn’t using that name any more). Mentor’s Vista is based on the OSCI TML 2.0 transaction-level modeling standard, which Mentor has adopted as a … Continue reading

Posted in Design, EDA, ESL, Low-Power | Tagged , , , | 1 Comment