Category Archives: DRAM

Imagine no uninterruptible power supplies. I wonder if you can. A sad story of six fried hard disk drives

This is the story of six fried hard disk drives and why they died needlessly of heat failure as told to me by my good friend Ron Sartore, founder and CEO of AgigA Tech, at this month’s Flash Memory Summit. … Continue reading

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Think Globally, Act in Parallel. What can you do with one million ARM cores acting in parallel and how do you get there?

Professor Steve Furber’s SpiNNaker project is in the news again. I wrote about Furber’s massively parallel brain-emulation project back on March 30 after listening to his keynote at this year’s DATE (Design Automation and Test Europe) conference in Grenoble, France. … Continue reading

Posted in ARM, CMOS, Design, DRAM, Low-Power, Networking, SDRAM, SOC, SRAM | Tagged , , , , , | Leave a comment

The DDR4 SDRAM spec and SoC design. What do we know now?

DDR4 SDRAM is coming. JEDEC may not have released the final spec yet but Samsung made the first DDR4 memory chip announcement in January of this year—a 2133MHz device built with a 30nm process technology—and Hynix followed suit in April … Continue reading

Posted in DDR4, DRAM, Low-Power, SOC | Tagged , , , | 2 Comments

Multicore server, PC, and embedded designs push memory power, drive use of advanced DDR3 SDRAMs

Systems designers try all sorts of methods to reduce system power consumption. For years, we’ve relied on circuit tricks and have been reducing logic supply levels from the 5V power supplies that were so common in from the 1970s and … Continue reading

Posted in Design, DRAM, Green Design, Low-Power, SDRAM | Tagged , | 4 Comments

SPMT engulfs LPDDR2 standard, making adoption a no-brainer. Meanwhile Marvell jumps on the bandwagon.

An insidious power problem has slowly crept up on embedded-system designers. While most of us were firmly focused on the power dissipation of our ever-expanding logic designs with their increasing number of processor cores in multicore designs, we mostly ignored … Continue reading

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Xilinx redefines the high-end microcontroller with its ARM-based Extensible Processing Platform – Part 1

Last week at the Embedded Systems Conference (ESC) held in San Jose, California, Xilinx disclosed additional information about its upcoming Extensible Processing Platform (EPP), which I previously discussed in a February 1 blog entry written just after RTECC (the Real … Continue reading

Posted in Design, DRAM, FPGA, Low-Power, SOC | Tagged , , , | 2 Comments

The Surprising Popularity Rise of On-Chip Memory

I attended the 7th International SOC Conference in Newport Beach last week and several of the speakers addressed issues relating to SOC and system power. One of these speakers was Bob Madge, Director of Technology Marketing at LSI Corp (formerly … Continue reading

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State-of-the-Art in Low-Power Memory: Denali’s MemCon

Need gobs of cheap RAM? Need it to operate at the lowest possible power? This blog’s for you. I attended Denali’s ninth annual MemCon conference a few days ago. It was three days of intensive discussion about the state of … Continue reading

Posted in DRAM, Flash, Low-Power, LPDDR, LPDDR2, SDRAM | Tagged , , , , | Leave a comment