Steve Leibson

The Surprising Popularity Rise of On-Chip Memory

November 8, 2009 on 4:53 pm | In CMOS, DRAM, Design, Low-Power, SOC | No Comments

I attended the 7^th International SOC Conference in Newport Beach last week and several of the speakers addressed issues relating to SOC and system power. One of these speakers was Bob Madge, Director of Technology Marketing at LSI Corp (formerly LSI Logic). In case you didn’t know, LSI has been evolving its business from its original focus on developing ASICs and SOCs for customers to a focus on programmable ASSPs (application-specific standard products) and custom silicon specifically aimed at the networking and storage markets. Madge’s first slide explained the reasoning: annual storage-capacity growth is a projected 49% per year and annual network-traffic growth is a projected 42% per year. Good growth numbers for a business to target.

To deliver competitive parts, LSI stays on top of IC design and manufacturing trends. One trend that caught LSI and the semiconductor industry by surprise has been the rapid growth in on-chip memory use. On-chip memory makes sense for two reasons. First and foremost, it provides better performance than off-chip memory because putting memory on the chip along with the logic circuitry eliminates two sets of off-chip drivers and receivers, which reduces power consumption for memory transactions. Second, on-chip logic can communicate with on-chip memory over extremely wide memory interfaces—pin count is not an issue if you stay on the chip. A wide memory interface reduces the number of transfers needed to move a given amount of data and lower transfer rates cut power as well.

However, merging logic and memory on one piece of silicon has always presented design and manufacturing issues. Bulk, high-volume, high-capacity memory manufacturing processes differ from logic manufacturing processes because the two processes must optimize different parameters. Memory processes emphasize low cost manufacturing and tend to have fewer metal layers than logic processes, which emphasize speed and on-chip connectivity. “Frequency, density, and power are always a challenge,” said Madge.

For example:

• Today’s network routers use 400-Mbit buffers. Switches need 512 Mbits of storage or more. In the future, said Madge, these devices will need as much as 1 Gbit of on-chip memory in multiple configurations.

• IP controllers used in network storage applications currently use 60 to 100 Mbits of cache memory. In the future, these devices will need 200 Mbits of memory or more.

• Media processors currently use 60 to 80 Mbits of memory running at 500 MHz. Future needs will be on the order of 100 to 200 Mbits of memory running at 600 to 700 MHz.

All of these examples demonstrate the coming challenges for fast, dense, on-chip memory.

LSI is looking at embedded (on-chip) DRAM and the use of 3D, through-silicon via technology for chip-to-chip stacking as ways of increasing the amount of on-chip memory. The company is doing this because it sees a continued and rapid rise in the amount of on-chip memory needed for its networking and storage chips.

Embedded DRAM cuts power because it uses a 1T (one-transistor) cell, which obviously improves density over a 4T or 6T static RAM cell. However, embedded DRAM also reduces static and dynamic power consumption because the fewer transistors use less power and leak less current than the greater number of transistors required to build the same amount of SRAM memory.

LSI is also investigating other power-saving features that become possible when you move memory onto the logic chip including a sleep mode for the memory, dual power rails, and low-voltage operation. However, said Madge, the biggest benefit appears to be a move to embedded DRAM because of the huge reduction in transistor counts.

State-of-the-Art in Low-Power Memory: Denali’s MemCon

June 30, 2009 on 4:06 pm | In DRAM, Flash, LPDDR, LPDDR2, Low-Power, SDRAM | No Comments

Need gobs of cheap RAM? Need it to operate at the lowest possible power? This blog’s for you.

I attended Denali’s ninth annual MemCon conference a few days ago. It was three days of intensive discussion about the state of the art in DRAM and Flash memory-the two mainstay memory technologies in use today. Surprisingly, NAND Flash memory is now the low-cost leader in terms of cost per bit, having passed by DRAM a few years ago. However, DRAM remains the mainstay memory for the vast number of designs and DDR SDRAM now rules as it becomes easier and easier to find microcontrollers and FPGAs with direct DDR interfaces and DDR controller and PHY IP for SOCs.

Memory power consumption as a percentage of system power consumption has grown with the rapid growth of memory-array size in all sorts of systems. A real eye opener at MemCon 09 was a chart on the power consumption of memory in server systems, where the large server memory arrays consume as much as 40% of the system power and the processor now consumes a mere 28%. Why is that important? It’s important because big server users like Google pay tens of millions of dollars each year in electrical power costs to run and to cool their server farms and 40% of a few tens of millions of dollars is, well, tens of millions of dollars.

Note that the current share-of-power percentages for servers don’t make processor power consumption unimportant-28% is still a big number-but the clear message is that server designers must now be far more concerned with memory power consumption because it’s a big part of the power puzzle. As embedded designs adopt large DDR memory DIMMs for bulk memory, the same sort of situation applies. Embedded designers must also be aware of the way their DRAM choices affect system power.

Marc Greenberg, Denali’s Director of Technical Marketing, gave a 2-hour tutorial on low-power DDR SDRAM on the first day of MemCon09. He threw up one slide that does a terrific job of putting all of the low-power SDRAM parts in perspective:

This slide shows the optimum type of SDRAM to use based on your design’s memory-capacity and speed requirements. I like this slide a lot because it helps you to pick from the wide array of DDR types and speeds. However, it seems that your selection job is about to become a lot simpler. Look what happens to the chart when you add in LPDDR2 memory:

LPDDR2 memory delivers the low-power goods by operating the SDRAM’s memory core and I/O at 1.2V, which is what you need to do to substantially cut memory power these days. Several manufacturers have announced LPDDR parts with I/O speeds to 400MHz/DDR800 and spec sheets for these parts are beginning to appear on DRAM vendor Web sites. LPDDR2 vendors with announced parts include Elpida, Hynix, Micron, and Nanya. Note that there’s also the possibility for existing LPDDR1 vendors to create parts that operate at 1.2V for similar power savings and that some of the soon-to-be-seen DDR3 parts may operate at 1.35V, which qualify them as low-power DRAMS.

In addition, there’s a spec for LPDDR2 non-volatile memory (LPDDR2-NVM) to allow LPDDR2 DRAM and Flash to be intermixed. The big advantage of Flash LPDDR2 is the very low standby power but Flash memory exhibits both read and write wear-out failure, so DRAM isn’t yet obsolete and you’ll likely need both memory types in your system design. The LPDDR2-NVM spec allows for I/O speeds to 533MHz/DDR1066 operation, but Greenberg says that the initial LPDDR2-NVM parts are likely to be slower than the maximum.