Category Archives: CMOS

Low-energy microprocessor operates 40nm transistors in near-threshold mode to run on 0.4V@1MHz

Late last month at ISSCC, Belgian research center imec and its affiliated Holst Centre in The Netherlands discussed a microprocessor that can run at 1MHz on a 0.4V power supply with the processor’s CMOS transistors operating in near-threshold mode. The … Continue reading

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What if 2.5D got really cheap? How would that affect low-power design?

Last week, silicon-interposer foundry Deca Technologies unstealthed. I found out from an article in the San Jose Mercury News and just published a blog about the announcement in my other blog, the EDA360 Insider. Deca is a subsidiary of Cypress … Continue reading

Posted in 2.5D, CMOS, Design, Flash, Low-Power | Leave a comment

Think Globally, Act in Parallel. What can you do with one million ARM cores acting in parallel and how do you get there?

Professor Steve Furber’s SpiNNaker project is in the news again. I wrote about Furber’s massively parallel brain-emulation project back on March 30 after listening to his keynote at this year’s DATE (Design Automation and Test Europe) conference in Grenoble, France. … Continue reading

Posted in ARM, CMOS, Design, DRAM, Low-Power, Networking, SDRAM, SOC, SRAM | Tagged , , , , , | Leave a comment

Need to cut IP power? (Who doesn’t?) “Press here” says Calypto

All SoCs are built with IP blocks. Some of those are legacy IP blocks. Some are purchased from other vendors. Some are developed in-house. All of them draw power—static and dynamic power. At nanometer lithographies, the way to cut static … Continue reading

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Tabula FPGA Scatters Logic, Memory, and Power Across Space and Time

Here’s a head-scratcher for you. Why not create tesseract FPGAs? A tesseract is the 4-dimensional version of a 3D cube. (Just as a 3D cube can be unfolded to make a set of six connected 2D squares, a tesseract can … Continue reading

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Intel cuts IC power by allowing, detecting, and correcting errors

The low-power IC-design train has long ridden the rails of lowered supply voltage. However, these lowered supply rails are tangentially approaching transistor threshold voltages and have long been headed for a serious collision because transistors in large, nanometer ICs run … Continue reading

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Laser Spike Annealing of Nickel in Nanometer CMOS ICs Cuts Leakage 10x

One of the sad facts of life for nanometer silicon has been the rise of leakage current as device geometries shrink. At 65nm, CMOS leakage currents roughly equal operating currents, making it virtually impossible to reduce overall operating current by … Continue reading

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The Surprising Popularity Rise of On-Chip Memory

I attended the 7th International SOC Conference in Newport Beach last week and several of the speakers addressed issues relating to SOC and system power. One of these speakers was Bob Madge, Director of Technology Marketing at LSI Corp (formerly … Continue reading

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Give OTP a chance for low-power, on-chip storage

The on-chip memories that get most of the attention are read/write memories such as SRAM, DRAM, Flash, and MRAM (which I just covered in my previous blog entry). However, there’s a place for OTP (one-time programmable) memory on chip, so … Continue reading

Posted in CMOS, Design, Flash, Hubble, Low-Power, Space, Uncategorized | Tagged , , , | Leave a comment

Could A Low-Power Middle Ground Between ASICs/SOCs and FPGAs Help You?

You can’t always get what you want, But if you try sometime, You’ll find, You get what you need. Those lyrics from a song from the Rolling Stones describes the situation with ASICs/SOCs and FPGAs. For low power, you want … Continue reading

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