2011 was a great year for low-power design. I don’t think I can remember a year as good to low-power designers and I thought I’d devote this second part of my blog post on this topic to review some major process and packaging technology advances that occurred this year, which I think will have major implications for years to come.
Perhaps the biggest process innovation to hit the semiconductor industry, with a long-tail effect on low-power semiconductor design, will turn out to be the 28nm process node. Here are the clues on which I’m basing this opinion.
First, Xilinx provided a very long and detailed explanation as to why it selected the TSMC 28nm HPL process technology for all three members of its series 7 FPGAs (Virtex-7, Kintex-7, and Artex-7) over the TSMC 28nm HP and P process technologies. The 28nm HP process variant is strictly for high-performance designs and the 28nm LP process variant, which employs PolySiON (polysilicon/silicon oxy-nitride) gate oxide, delivers low leakage but also lower-performance transistors. The 28nm HPL process variant is a high-K metal-gate technology that produces high-speed, low-leakage transistors. (See “Xilinx 28nm low-power SoC design class, part 2: Process Technology”)
It’s not Xilinx’ selection of the 28nm HPL process that’s the highlight here—it’s the fact that there are two low-power variants of the 28nm process available to IC design teams. They have the flexibility to pick the process variant that best meets the objectives for a specific IC.
Altera took a different approach in developing a low-power FPGA based on 28nm process technology. Late last month, the company announced that it had started shipping low-power Arria V FPGAs based on the TSMC 28nm LP process variant because it allows the Arria V FPGA family to deliver “the lowest total power, lowest static power, and lowest transceiver power of any midrange FPGA family, consuming up to 40% less power compared to previous generation devices.”
It’s this flexibility in 28nm process variants that I think will allow all sorts of interesting low-power design techniques to be used in future products designed with 28nm process technology. And the 28nm process node is critically important for another reason: It appears to be the last process node to be manufactured without taking extraordinary measures in lithography. By that, I mean that after the 28nm node, we will be seeing a big bump in lithographic complexity, first through double, triple, and quadruple patterning and then through EUV (extreme ultraviolet, aka X-rays) lithography. Scaling is about to get much more difficult after 28nm.
3D IC Assembly
Which leads me to the other big semiconductor manufacturing innovation whose time has apparently arrived: 3D IC assembly. I believe that the time has arrived for 3D IC assembly to become mainstream and that we will see a revolution in SoC design and development based on adding 3D design to the mix. There are just too many benefits to ignore and I discussed some of these in my previous blog post (Part A).
To recap, the big advantages are:
- A huge reduction in I/O power to transfer signals from chip to chip
- A huge increase in chip-to-chip bandwidth without increasing I/O power consumption or packaging costs
- Ability to intermix logic, memory, analog, and RF functions by implementing them on separately optimized die (using separately optimized process technologies) and then creating appropriate 3D assemblies
- Cost advantages by reducing average die size
- Reduction in pressure to jump to the next process node (and higher design and NRE costs) by providing an alternative path to SoC-level integration
These advantages cannot be ignored and indeed companies are not ignoring them. TSMC itself has already stepped in and proposed itself as a 1-stop shop for IC die manufacture and 3D assembly. (See “3D Week: The State of 3D IC assembly—December 2011”) Xilinx is already solidly in the 2.5D IC assembly camp with the Virtex-7 2000T FPGA and you can bet that technology will make its way down the product line as quickly as the costs of early adoption can be reduced.
JEDEC has announced the finalization of the Wide I/O SDRAM specification, which is essential to the development of 3D memory stacks with high-speed, low-power data-transfer features. (See “3D Week: JEDEC Wide I/O Memory spec cleared for use”
The economics of the entire industry now solidly point to the adoption of 3D IC assembly as a mainstream packaging technology. (See “3D Week: Driven by economics, it’s now one minute to 3D”) Between the increasing availability of 28nm process technology and the rise of 3D IC assembly, I see a new flowering of electronic design the likes of which we have not seen since the early 1990s, when surface-mount technology and ASIC design both came of age nearly simultaneously. That was truly an great era for the industry. The same sort of simultaneous advance in semiconductor and packaging technology is taking place with 28nm process technology and 3D IC assembly.
It’s a great time for low-power design.