Monthly Archives: June 2011

Cadence’s Qi Wang discusses the use of good methodology for low-power, advanced IC designs

You can read Qi Wang’s writeup of a paper on low-power IC design presented by Global Unichip’s Alex Kuo here.

Posted in Low-Power | Tagged , | Leave a comment

Richard Goering discusses the low-power aspects of 40nm and 28nm design with Global Unichip’s Alex Kuo

Cadence blogger and long-time EDA editor Richard Goering spent some time at the recent DAC event in San Diego discussing the finer points of 40nm and 28nm design with Global Unichip’s Alex Kuo. Among the interesting tidbits from the interview … Continue reading

Posted in Low-Power | Tagged , | Leave a comment

Need to cut IP power? (Who doesn’t?) “Press here” says Calypto

All SoCs are built with IP blocks. Some of those are legacy IP blocks. Some are purchased from other vendors. Some are developed in-house. All of them draw power—static and dynamic power. At nanometer lithographies, the way to cut static … Continue reading

Posted in Clock Gating, CMOS, Design, EDA, Low-Power, SRAM | Tagged , | Leave a comment

IBM Researchers Develop Planar, Monolithic, 1-Transistor Graphene IC—Make Graphene Party Like It’s 1959

This week in Science Magazine, IBM researchers published an article documenting the first graphene IC built using recognizable IC processing techniques. The simple 1-transistor, 2-inductor monolithic circuit operates as an RF mixer with a useful operating frequency of 10GHz. The … Continue reading

Posted in Graphene | Tagged | Leave a comment

The Return of Heathkit (in spirit) at Maker Faire

I visited the most recent edition of Maker Faire last month and from what I can see, the event just keeps rolling along. I think it’s exciting to be in the company of people who love to make things. Anything. … Continue reading

Posted in Low-Power | Tagged , , , | Leave a comment