After telegraphing its punch at ESC last spring, Xilinx has now introduced the first four members of its EPP product line and named them Zynq to differentiate them from the company’s FPGAs. (See “Xilinx redefines the high-end microcontroller with its ARM-based Extensible Processing Platform – Part 1” and “Xilinx redefines the high-end microcontroller with its ARM-based Extensible Processing Platform – Case Studies – Part 2”.) Two of the four Zynq family members are designed for low-power applications and the other two emphasize performance over power. “What’s an EPP?” you might ask. It’s an “Extensible Processing Platform,” a new IC category Xilinx hopes to create. Think of an EPP as an embedded processor with an attached FPGA fabric. “Haven’t they tried this before?” you’re now asking. Yes, they have. This time, the difference is that Xilinx is emphasizing the “processor” aspect of the device over the FPGA aspect—and you can expect that change in emphasis to make all the difference.
The Xilinx Zync EPP family is designed to wedge in between ASICs or SoCs, microcontrollers, and FPGAs. What Xilinx has done is leverage its 28nm expertise—earned from its development of the company’s Artix/Kintex/Virtex-7 FPGAs—and used that expertise to develop a new type of product that’s mostly hardened processor cores (with associated memory and peripherals) and then added a layer of FPGA fabric, like icing on a cake, to produce a new confection. With the smaller Zynq parts selling for less than $15 in volume, these confections will clearly catch the eye of many, many system designers trying to get the most bang for their silicon buck. Zynq EPPs will be available in first silicon starting in the second half of 2011 with general engineering samples available in 1H2012.
Here’s a family block diagram of the Xilinx Zynq EPPs:
At their hearts, each of the four Xilinx Zynq EPPs is a dual-core embedded processor based on two 800MHz ARM Cortex-A9 processors. Each processor is augmented with a copy of ARM’s NEON SIMD engine, a double-precision floating-point unit, 32 Kbytes of instruction cache, and 32 Kbytes of data cache. The two processor cores share a 512Kbyte unified L2 cache. Separate memory controllers, one for DRAM and one for Flash, connect the processor cores to external memory. You need two controllers because DDR DRAMs and Flash devices require radically different control algorithms for optimum operation.
There are a large number of additional peripherals on these chips—all in hard-core form—including two Gigabit Ethernet controllers; two USB 2.0 ports (with USB On-The-Go capability); two SDIO ports for talking to SD Flash media cards; two UARTs; two CAN bus controllers for automotive applications; two 12-bit 1Msample/sec A/D converters with 17 analog inputs; two I2C ports and two SPI ports for talking to serial peripherals; some GPIO pins for whatever else you need to talk to; and an 8-channel DMA controller to move data around the chip.
So far, the Zynq EPPs look like very nice, dual-core embedded processors. What happens next is part of Xilinx’ strategy to create an entirely new product category. Using the ARM AMBA 4 AXI4 interconnect as a connection matrix, Xilinx has driven four 32-bit and four 64-bit AXI4 ports into a block of FPGA fabric. The point of the included FPGA fabric is to allow system designers to create peripheral devices not already on the chip in hard-core form. (Note, Cadence introduced a new verification IP catalog with an AMBA4 VIP model just yesterday.)
The actual FPGA fabric capacity included on the Zynq EPPs ranges from 30,000 to 235,000 logic cells, depending on the Zynq family member. Xilinx will tell you that those logic-cell capacities are approximately equivalent to 430,000 to 3.5 million ASIC gates. How did Xilinx get these equivalent numbers? By multiplying by 15. Where did “15” come from? It’s an average, derived from the observation that one logic cell appears to do the job of 10 to 20 ASIC gates across a range of designs. Are the “ASIC gates” equivalencies accurate? Looks like plus or minus 33% to me. The Zynq FPGA fabrics also house block RAMs ranging in capacity from 240 Kbytes to 1.86 Mbytes and they include the usual MACs now commonly found in FPGA fabrics.
Each AMBA4 AXI4 port that bridges the processor complex to the FPGA fabric has a dual arbiter to handle simultaneous accesses from the various masters on the chip. A ninth port, based on the ARM Cortex-A9 ACP (accelerator coherency port) connects the processors’ snoop control unit to the FPGA fabric. The ACP provides a device, such as an external DMA controller, with direct access to CPU-coherent data regardless of where the data is in the CPU cache and memory hierarchy.
The two members of the Zynq family designed for low-power applications incorporate an FPGA fabric based on Xilinx’ Artix-7 FPGAs and the two high-performance members of the Zynq family incorporate an FPGA fabric based on the company’s Kintex-7 FPGAs. The two high-performance Zynq devices also sport either four or twelve 10.3Gbps serial transceiver channels and a PCIe Gen2 controller (4- or 8-lane depending on the Zynq family member).
Notably, it’s the hard-core processor section of the Zynq device that powers up first after a reset, which allows the OS to boot and some of the application code to start executing. This is a familiar environment for any embedded software team. After the processors are up and running, the code can then configure the FPGA fabric.
Here’s a table of the key attributes for the four initial members of the Xilinx Zynq EPP family:
Enough about the Zynq silicon. The development tools are equally important for such an extensively programmable and configurable device. Xilinx will be providing a $495, Eclipse-based Platform Studio Software Development Kit for the Zynq family. The on-chip ARM Cortex-A9 processor cores open the wide world of ARM’s development ecosystem is open to design teams using Zynq parts.
There are at least a couple of alternatives for developing peripheral blocks in the Zynq EPP FPGA fabrics. The Xilinx ISE Design Suite is the company’s standard FPGA development environment so any designer accustomed to developing logic designs with Xilinx FPGAs will feel at home. The design suite includes both development tools and plug-and-play peripheral IP with AMBA4 AXI4 interfaces that can be dropped into place on the chips. Xilinx has standardized on the AMBA4 AXI4 interconnect standard for its IP block interfaces for both EPPs and FPGAs. Hence the eight AMBA4 AXI4 ports on the Zynq parts. The Xilinx IP blocks also include bus-functional models for system simulation.
Xilinx has created a compelling value proposition with the new Zynq EPPs. It’s quite common for system-design teams to couple some sort of embedded processor with an FPGA in many designs that haven’t the volume needed to justify the design of a custom SoC. The Zynq EPPs offer yet another alternative—one that merges a dual-core embedded processor with a state-of-the-art FPGA fabric and connects the two with a high-bandwidth connection. Moreover, the Xylinx Zynq EPPs give system designers access to 28nm process technology at a relatively low component cost, low NRE (no need to redesign the processor complex), and zero mask and fab costs.
This mixture of capability, performance, and cost simply cannot be replicated with a 2-chip design. Going forward, few system-design teams will be able to avoid at least considering Zynq EPPs in their preliminary architectural explorations. Sure, if you’re building a mobile telephone handset, then a Zynq EPP clearly isn’t for you. If a low-cost microcontroller selling for a buck or so will do the job, that’s an obvious right choice. Custom SoCs still win the day for high-volume, low-power, high-performance applications. For in-between system designs, Zynq EPPs seem like they’re going to be mighty attractive.