NOCs: The Undead of the SOC World

The 7th International SOC Conference in Newport Beach featured a session on NOCs (networks on chip). Perhaps it’s the undue influence of the recent Halloween festivities, but NOCs remind me of vampires, of the undead. They just keep coming back no matter what, despite the lack of uptake in the commercial sector.

Academics love NOCs because they can be analyzed to death and they provide wonderful fodder for postgraduate work. You can come up with increasingly elegant, time-consuming, and costly routing algorithms for NOCs, which has permitted the creation of many, many academic papers. Each and every paper lists the prior failings of earlier NOC approaches, analyzes the shortcomings, and then proposes an even more elegant and costly NOC that solves the technical problems of predecessors. But these more elegant solutions have even less commercial potential because of the costs.

When will it end?

Perhaps never.

One of the speakers at last week’s International SOC Conference was Professor Nader Bagherzadeh of UC Irvine’s EECS Department. His presentation was sensibly titled “Is Network-on-Chip (NoC) a Viable Choice for the Future?” That’s a very reasonable question and Processor Bagherzadeh gave a reasoned presentation. One of his first slides contrasted three approaches to SOC interconnect design. The first approach, popular with most of today’s SOC designers, is the use of bus hierarchies.

Buses are the dinosaurs of system design. The fossils of bus-based, board-level designs from decades past form the bones of new SOC designs even though the economics of on-chip nanometer silicon interconnect now bear no resemblance to the copper-and-fiberglass design rules and economics of the 1980s. As Processor Bagherzadeh said, bus-based designs are not scalable, they enforce centralized control in increasingly decentralized systems of growing complexity, and they force the use of long wires on the SOC, which severely degrades performance and needlessly exposes system designs to the newest bugaboo for deep-submicron design: on-chip variability.

The current leader for efficient, fast SOC designs is point-to-point interconnect, which offers low latency, application-specific optimization, very high bandwidth, and low cost. Deep-submicron wires are plentiful and cheap. System designers should use them accordingly.

And then there are NOCs, which also promise shorter wiring runs between on-chip routers. High levels of interconnectivity mean that NOCs can provide high bandwidth with distributed traffic control. However, said Processor Bagherzadeh, NOCs are not as efficient as point-to-point wiring for carrying traffic on application-specific SOCs and consequently we have still not seen many tapeouts that use NOCs for real chips in real applications.

But that doesn’t mean that NOCs are elegantly useless. I think Processor Bagherzadeh made a good case for NOCs to be used as flexible interconnect when designing a platform chip. Here, you don’t have all of the knowledge to predict traffic flows over an entire chip and need some flexibility when routing high-bandwidth traffic. In such cases, you might be willing to suffer the silicon overhead of a NOC in exchange for interconnect flexibility.

It was at that point that Processor Bagherzadeh started to discuss his work with a 7-channel NOC router, which is even bigger, better, and more elegant than the conventional 5-port NOC router, offers more effective traffic bandwidth and throughput, and requires even more elegant routing algorithms. We now return you to our regular NOC programming where the usual solution to low uptake in NOC usage is to create bigger, better, and more elegant NOC hardware and routing algorithms.

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3 Responses to NOCs: The Undead of the SOC World

  1. Theo says:


    You are right, there is a lot of academic nonsense published on NoCs. By the way, academics tend not to restrict themselves to NoCs when it goes about publishing nonsense.

    Nonetheless I found your post a little unfair to the commercial success of NoC companies such as Arteris or Sonics. Their IPs are used in mainstream SoCs. There is even a fair chance you have a NoC in your mobile phone.

    Arteris NoC used in TI’s OMAP 65nm and 45nm platforms:

    Sonics NoC selected by Toshiba:


  2. sleibson321 says:

    Theo, are you objecting to me quoting the professor or do you find the phrase “not very many tapeouts” to be unfair to NOCs. In the first case, the professor said what he said. In the second, citing less than a handful of SOC designs with NOCs hardly alters the view that “not many tapeouts” have occurred.

  3. fferro says:


    Thanks for your NoC analysis. It shows good insight into the practical use of today’s NoC technology. At Sonics we use the phrase “Moving SoC design beyond the NoC” to allude to many of the same points you mention in your blog (see my blog For practical SoC design implementations, there are elements of pure NoC technology that can be useful. This is especially true now that the pace and complexity of SoC design have increased — with companies moving aggressively to 45nm technology and below. The number of heterogeneous cores in today’s SoCs can easily exceed 50 — and even up to well over 100 cores. Given the connectivity requirements of these chips, the scalability of the NoC can be useful for cores in the system that can deal with longer latencies. Having said this, I do not foresee any SoCs that will use NoC topology to satisfy 100% of the connectivity requirements. SoC designers need a comprehensive ‘tool box’ of on-chip connectivity solutions to efficiently reconcile the trade-offs between performance, gate count and power. The NoC is one of several important elements in that tool box. The future of SoC design is indeed moving well beyond the “NoC” technology we have previously known (in academia) into combining the best mix of on-chip network technologies to solve real connectivity challenges.

    Frank Ferro
    Director, Business Development
    Sonics, Inc.

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