Yesterday, I moderated a panel on green chip design in Newport Beach at the 7th International SOC Conference. Chances are you didn’t see or hear any of it because there were only 100 people at this conference in total. That’s really too bad because we had a great set of panelists:
1. Michel Laurence co-founded Octasic, which is a Montreal specialist in echo cancellation and has mastered the art of self-clocking or self-timed (asynchronous) logic design.
2. Jauher Zaidi, CEO, PalmChip Corporation, which was in the chip-design business but has now spun off those activities to focus more on SOC platform software.
3. Alan Ruberg, SPMT architect for SPMT, The Serial Port Memory Technology consortium, which is developing a high-performance, low-power, next-generation memory interface to replace the DDR families with an interface that uses fewer pins.
4. Dr. Simiack Haghighi, Principal Architect of Qualcomm’s CDMA Technology Architecture Group, which should need no introduction…and
5. Steve Carlson, VP of Product Marketing at Cadence (who kindly volunteered from the audience at the last minute when a panelist from another leading EDA company didn’t show).
I tossed out questions from readers of my blogs, some I developed on my own, and some that came from the panelists themselves. Here’s the first question and the panelists’ answers.
This was a cynical question from one of my blog readers: What’s the difference between the design of a Green Chip and one of those greyish Silicon ones?….More to my point – doesn’t Darwin take care of those companies who don’t design to a lower power solution than their competitors and, therefore, is this “Green Chip” thing just hopping aboard the Hype Bandwagon?
Cadence’s Steve Carlson quickly snagged this first question. His cool reply was that the industry’s focus on green technology has little to do with tree hugging. It’s all about business. The confluence of business issues such as cost and power and the social issues that draw the general press coverage, but business drives the design decisions.
Palmchip’s Jauher Zaidi agreed. There’s lots of hype about “green” these days, he said, but cost drives everything. Energy costs drive purchasing decisions at data centers, which use a lot of electrical power. Chip-design teams need power engineers now, he concluded.
SPMT’s Alan Ruberg also chimed in for this first question. Every Watt dissipated by a system requires another Watt in cooling, he said. So every Watt you save in a design delivers a 2-for-1 return in terms of energy savings. He added “By the year 2020, if trends continue on the present course, you’ll only be able to power 9% of a chip at any given time.”
How can that be? Why not just omit the other 91% of the design? Because all of the panelists can foresee a time in the rapidly approaching future when there will be specialized blocks for all the tasks performed by a chip, but not all tasks need be running simultaneously. For example, a mobile handset chip with functional blocks for a still camera and a video camera need power up only one of those blocks at a time because they share the lens and cannot operate simultaneously, yet they each require different optimizations so it makes sense to design special-purpose blocks (or get the relevant predesigned IP) for both functions and then power the one that’s needed.
There were some interesting independent observations that I noted in addition to the answers to the questions asked during the panel session:
Palmchip’s Jauher Zaidi noted that Amdahl’s Law applies to the power component of systems as well as to its usual application for analyzing execution time. It does no good to reduce the power of one system block by 10x in a system like the iPhone, for example, if it represents only a small part of the overall system power consumption. You end up reducing the system’s energy consumption very little. Power reduction requires a systemic approach.
Zaidi also noted that he needs to charge his iPhone three times a day and that he also manually turns functions on and off to extend battery life. He recommended that designers make it easier for users to manage their increasingly complex devices. I countered, saying that my kitchen doesn’t require such management. The microwave oven doesn’t turn itself on spontaneously and the refrigerator turns itself on and off automatically to maintain set temperatures. Surely we can manage more of the functions in today’s more intelligent systems in a… more intelligent manner. I submit that we’re better off trying to engineer smarter systems than smarter customers. Social engineers we’re not.
Cadence’s Steve Carlson estimated that less than one third of SOC designs today use DVFS (dynamic voltage and frequency scaling) and 10% or more don’t even use clock gating. Those are pretty dismal numbers in my opinion for practices that reduce an SOC’s power consumption and are known to work well.
Carlson noted that there’s lots of room for improvement.