Steve Leibson

Free White Paper on NAND Flash from Denali

NAND Flash manufacturing cost reductions of 60% per year sustained over nearly a decade have driven many technology changes, developments, compromises, and innovations. Prices have fallen even faster over the past five years, but the precipitous price decline could easily slow due to technical forces and in all likelihood, they will. Further, NAND Flash specifications are changing and will continue to change in predictable and unpredictable ways due to these forces. These changes will create new capabilities for NAND users, will impose extra performance burdens, and may ultimately limit the flexibility of NAND Flash in future device generations compared to what is available today.

This paper describes these trends in a series of warnings, enumerates the steps the semiconductor industry is taking to smooth product transition for NAND Flash users, and highlights developments that may create problems for NAND Flash users in the immediate future. NAND Flash trends discussed in this paper include:

• Page-size trends and their impact on NAND devices and controllers
• Changes to the spare area on NAND Flash devices
• Changing page architectures and ways to use the new architectures
• Increasing bit error rates and the associated rise in error correction code (ECC) complexity

NAND Flash manufacturers employ a broad variety of technology roadmaps, semiconductor implementation methodologies, and cost/performance optimization-and-tradeoff strategies to develop and manufacture NAND Flash devices. Diverse applications for NAND Flash memories drive similarly diverse performance specifications and requirements. “One Technology Roadmap Does Not Fit All” is an important guiding principle here. Consequently, products from some NAND Flash vendors may take somewhat different approaches to those described in this paper even though the vendors are responding to the same technical and market pressures considered below.

NAND-Flash controller designers may find the warnings and comments in this paper useful as they analyze important trends in NAND Flash management. In particular, advanced NAND Flash devices need extensive software management and error-correcting methodologies to create fully-functional memory subsystems that provide error-free data storage and they’ll need even more management and better ECC methodologies in the near future. From Denali. http://j.mp/tAjUo

NOCs: The Undead of the SOC World

The 7^th International SOC Conference in Newport Beach featured a session on NOCs (networks on chip). Perhaps it’s the undue influence of the recent Halloween festivities, but NOCs remind me of vampires, of the undead. They just keep coming back no matter what, despite the lack of uptake in the commercial sector.

Academics love NOCs because they can be analyzed to death and they provide wonderful fodder for postgraduate work. You can come up with increasingly elegant, time-consuming, and costly routing algorithms for NOCs, which has permitted the creation of many, many academic papers. Each and every paper lists the prior failings of earlier NOC approaches, analyzes the shortcomings, and then proposes an even more elegant and costly NOC that solves the technical problems of predecessors. But these more elegant solutions have even less commercial potential because of the costs.

When will it end?

Perhaps never.

One of the speakers at last week’s International SOC Conference was Professor Nader Bagherzadeh of UC Irvine’s EECS Department. His presentation was sensibly titled “Is Network-on-Chip (NoC) a Viable Choice for the Future?” That’s a very reasonable question and Processor Bagherzadeh gave a reasoned presentation. One of his first slides contrasted three approaches to SOC interconnect design. The first approach, popular with most of today’s SOC designers, is the use of bus hierarchies.

Buses are the dinosaurs of system design. The fossils of bus-based, board-level designs from decades past form the bones of new SOC designs even though the economics of on-chip nanometer silicon interconnect now bear no resemblance to the copper-and-fiberglass design rules and economics of the 1980s. As Processor Bagherzadeh said, bus-based designs are not scalable, they enforce centralized control in increasingly decentralized systems of growing complexity, and they force the use of long wires on the SOC, which severely degrades performance and needlessly exposes system designs to the newest bugaboo for deep-submicron design: on-chip variability.

The current leader for efficient, fast SOC designs is point-to-point interconnect, which offers low latency, application-specific optimization, very high bandwidth, and low cost. Deep-submicron wires are plentiful and cheap. System designers should use them accordingly.

And then there are NOCs, which also promise shorter wiring runs between on-chip routers. High levels of interconnectivity mean that NOCs can provide high bandwidth with distributed traffic control. However, said Processor Bagherzadeh, NOCs are not as efficient as point-to-point wiring for carrying traffic on application-specific SOCs and consequently we have still not seen many tapeouts that use NOCs for real chips in real applications.

But that doesn’t mean that NOCs are elegantly useless. I think Processor Bagherzadeh made a good case for NOCs to be used as flexible interconnect when designing a platform chip. Here, you don’t have all of the knowledge to predict traffic flows over an entire chip and need some flexibility when routing high-bandwidth traffic. In such cases, you might be willing to suffer the silicon overhead of a NOC in exchange for interconnect flexibility.

It was at that point that Processor Bagherzadeh started to discuss his work with a 7-channel NOC router, which is even bigger, better, and more elegant than the conventional 5-port NOC router, offers more effective traffic bandwidth and throughput, and requires even more elegant routing algorithms. We now return you to our regular NOC programming where the usual solution to low uptake in NOC usage is to create bigger, better, and more elegant NOC hardware and routing algorithms.

The Surprising Popularity Rise of On-Chip Memory

I attended the 7^th International SOC Conference in Newport Beach last week and several of the speakers addressed issues relating to SOC and system power. One of these speakers was Bob Madge, Director of Technology Marketing at LSI Corp (formerly LSI Logic). In case you didn’t know, LSI has been evolving its business from its original focus on developing ASICs and SOCs for customers to a focus on programmable ASSPs (application-specific standard products) and custom silicon specifically aimed at the networking and storage markets. Madge’s first slide explained the reasoning: annual storage-capacity growth is a projected 49% per year and annual network-traffic growth is a projected 42% per year. Good growth numbers for a business to target.

To deliver competitive parts, LSI stays on top of IC design and manufacturing trends. One trend that caught LSI and the semiconductor industry by surprise has been the rapid growth in on-chip memory use. On-chip memory makes sense for two reasons. First and foremost, it provides better performance than off-chip memory because putting memory on the chip along with the logic circuitry eliminates two sets of off-chip drivers and receivers, which reduces power consumption for memory transactions. Second, on-chip logic can communicate with on-chip memory over extremely wide memory interfaces—pin count is not an issue if you stay on the chip. A wide memory interface reduces the number of transfers needed to move a given amount of data and lower transfer rates cut power as well.

However, merging logic and memory on one piece of silicon has always presented design and manufacturing issues. Bulk, high-volume, high-capacity memory manufacturing processes differ from logic manufacturing processes because the two processes must optimize different parameters. Memory processes emphasize low cost manufacturing and tend to have fewer metal layers than logic processes, which emphasize speed and on-chip connectivity. “Frequency, density, and power are always a challenge,” said Madge.

For example:

• Today’s network routers use 400-Mbit buffers. Switches need 512 Mbits of storage or more. In the future, said Madge, these devices will need as much as 1 Gbit of on-chip memory in multiple configurations.

• IP controllers used in network storage applications currently use 60 to 100 Mbits of cache memory. In the future, these devices will need 200 Mbits of memory or more.

• Media processors currently use 60 to 80 Mbits of memory running at 500 MHz. Future needs will be on the order of 100 to 200 Mbits of memory running at 600 to 700 MHz.

All of these examples demonstrate the coming challenges for fast, dense, on-chip memory.

LSI is looking at embedded (on-chip) DRAM and the use of 3D, through-silicon via technology for chip-to-chip stacking as ways of increasing the amount of on-chip memory. The company is doing this because it sees a continued and rapid rise in the amount of on-chip memory needed for its networking and storage chips.

Embedded DRAM cuts power because it uses a 1T (one-transistor) cell, which obviously improves density over a 4T or 6T static RAM cell. However, embedded DRAM also reduces static and dynamic power consumption because the fewer transistors use less power and leak less current than the greater number of transistors required to build the same amount of SRAM memory.

LSI is also investigating other power-saving features that become possible when you move memory onto the logic chip including a sleep mode for the memory, dual power rails, and low-voltage operation. However, said Madge, the biggest benefit appears to be a move to embedded DRAM because of the huge reduction in transistor counts.

Green Chips in Newport Beach

Yesterday, I moderated a panel on green chip design in Newport Beach at the 7th International SOC Conference. Chances are you didn’t see or hear any of it because there were only 100 people at this conference in total. That’s really too bad because we had a great set of panelists:

1. Michel Laurence co-founded Octasic, which is a Montreal specialist in echo cancellation and has mastered the art of self-clocking or self-timed (asynchronous) logic design.
2. Jauher Zaidi, CEO, PalmChip Corporation, which was in the chip-design business but has now spun off those activities to focus more on SOC platform software.
3. Alan Ruberg, SPMT architect for SPMT, The Serial Port Memory Technology consortium, which is developing a high-performance, low-power, next-generation memory interface to replace the DDR families with an interface that uses fewer pins.
4. Dr. Simiack Haghighi, Principal Architect of Qualcomm’s CDMA Technology Architecture Group, which should need no introduction…and
5. Steve Carlson, VP of Product Marketing at Cadence (who kindly volunteered from the audience at the last minute when a panelist from another leading EDA company didn’t show).

I tossed out questions from readers of my blogs, some I developed on my own, and some that came from the panelists themselves. Here’s the first question and the panelists’ answers.

This was a cynical question from one of my blog readers: What’s the difference between the design of a Green Chip and one of those greyish Silicon ones?….More to my point – doesn’t Darwin take care of those companies who don’t design to a lower power solution than their competitors and, therefore, is this “Green Chip” thing just hopping aboard the Hype Bandwagon?

Cadence’s Steve Carlson quickly snagged this first question. His cool reply was that the industry’s focus on green technology has little to do with tree hugging. It’s all about business. The confluence of business issues such as cost and power and the social issues that draw the general press coverage, but business drives the design decisions.

Palmchip’s Jauher Zaidi agreed. There’s lots of hype about “green” these days, he said, but cost drives everything. Energy costs drive purchasing decisions at data centers, which use a lot of electrical power. Chip-design teams need power engineers now, he concluded.

SPMT’s Alan Ruberg also chimed in for this first question. Every Watt dissipated by a system requires another Watt in cooling, he said. So every Watt you save in a design delivers a 2-for-1 return in terms of energy savings. He added “By the year 2020, if trends continue on the present course, you’ll only be able to power 9% of a chip at any given time.”

How can that be? Why not just omit the other 91% of the design? Because all of the panelists can foresee a time in the rapidly approaching future when there will be specialized blocks for all the tasks performed by a chip, but not all tasks need be running simultaneously. For example, a mobile handset chip with functional blocks for a still camera and a video camera need power up only one of those blocks at a time because they share the lens and cannot operate simultaneously, yet they each require different optimizations so it makes sense to design special-purpose blocks (or get the relevant predesigned IP) for both functions and then power the one that’s needed.

There were some interesting independent observations that I noted in addition to the answers to the questions asked during the panel session:

Palmchip’s Jauher Zaidi noted that Amdahl’s Law applies to the power component of systems as well as to its usual application for analyzing execution time. It does no good to reduce the power of one system block by 10x in a system like the iPhone, for example, if it represents only a small part of the overall system power consumption. You end up reducing the system’s energy consumption very little. Power reduction requires a systemic approach.

Zaidi also noted that he needs to charge his iPhone three times a day and that he also manually turns functions on and off to extend battery life. He recommended that designers make it easier for users to manage their increasingly complex devices. I countered, saying that my kitchen doesn’t require such management. The microwave oven doesn’t turn itself on spontaneously and the refrigerator turns itself on and off automatically to maintain set temperatures. Surely we can manage more of the functions in today’s more intelligent systems in a… more intelligent manner. I submit that we’re better off trying to engineer smarter systems than smarter customers. Social engineers we’re not.

Cadence’s Steve Carlson estimated that less than one third of SOC designs today use DVFS (dynamic voltage and frequency scaling) and 10% or more don’t even use clock gating. Those are pretty dismal numbers in my opinion for practices that reduce an SOC’s power consumption and are known to work well.

Carlson noted that there’s lots of room for improvement.

Amen.

A Low-Power, ARM-based Microcontroller from Oslo with a Winning Presentation

Last month at the ARM Techcon 3 conference, I watched as the CEO of a Norwegian fabless semiconductor company named Energy Micro leapt on stage, imitated Tom Cruse in his Mission Impossible role, opened his black-and-silver attache case, and announced the company’s EFM32 low-power microcontroller based on an ARM Cortex-M3 processor core. What really impressed me was not the over-amped Mission Impossible intro video or the bright green neckties that served as the company uniform at the conference. No, I was impressed by the strikingly graphical way the Energy Micro marketing crew came up with to demonstrate why their microcontroller has the lowest power. I was impressed enough to go through those slides here with you. See if you don’t agree with me about the effectiveness of this graphical presentation.

This first slide shows a power consumption profile curve for a microcontroller as it wakes up, does its thing, and then goes back to sleep. The area shown under the curve is the total expended energy for this profile. Reduce the area under the curve and you’ve cut energy consumption. Are you with me so far?

The first and most obvious thing to do to cut energy consumption is reduce the amount of power drawn by the microcontroller while it’s running in active mode. At 3V and with a 25 to 35 MHz clock, Energy Micro’s EFM32 consumes 180 microamps/MHz when executing code from internal Flash memory. At 3V and 1 MHz, the current consumption is 220 microamps/MHz. (In other words, at 1 MHz the current consumption is 220 microamps.)

The next step towards reducing the microcontroller’s energy consumption is to use a processor core that executes code efficiently so that the microcontroller spends less time in active mode. The EFM32 employs a 32-bit ARM core, which is way more efficient than older 8- and 16-bit microcontroller processor architectures at performing today’s more advanced tasks, so tasks can be executed more quickly—in fewer clock cycles.

Next, you need to deal with the energy consumed between the time the processor starts to wake up from sleep mode and the time it starts executing code. This is dead time when the processor isn’t doing anything useful (just like in sleep mode). However, during this time the microcontroller draws way more current than it does in sleep mode and that power is essentially wasted with respect to “getting the work done.” Some processors don’t wake up very fast, so they waste a non-negligible amount of power between the time they exit sleep mode and the time they start to execute code. The EFM32 wakes up its deep-sleep and stop modes in 2 microseconds, which appears to be relatively fast for this sort of thing compared to the numbers for competing processors in Energy Micro’s ARM Techcon 3 presentation.

In both of these modes, the EFM32 draws less than one microamp of current. The difference between the modes is that in deep-sleep mode, various low-frequency (32-KHz) peripherals continue to operate and can wake the processor. In stop mode, only interrupts, the I2C interface, and the on-chip analog comparators can wake the processor.

Because many embedded applications that have extremely low power and energy consumption requirements tend to put processors to sleep most of the time, it’s critical that the microcontroller have extremely low current consumption during its deepest sleep mode. The EFM32’s shutoff-mode current rating is a mere 20 nanoamps but it takes the processor 160 microseconds to come out of this mode, versus 2 microseconds for the lesser sleep modes. However, with 20 nanoamps of current consumption, the dirt on the board could consume more current than the processor through surface leakage if you’re not careful in cleaning the circuit board.

You need to assert the reset pin to bring the EFM32 out of shutoff mode so there are four other operating modes (stop, deep sleep, sleep, and run) with increasing levels of on-chip activity and increasing amounts of current consumption (from 0.6 microamps/MHz to 180 microamps/MHz).

What do you get by nibbling away various rectangles from the area under the original power-profile curve? You get a processor that might be able to run for more than 4 years from a CR2032 coin cell, which is longer than competing microcontrollers according to Energy Micro.

But wait, there’s more! The EFM32 sports “smart” autonomous peripherals, so the internal ARM Cortex-M3 processor core can spend even more time sleeping and less time working. The EFM32’s intelligent peripherals, which can be time- or data-triggered, include a 6-to-12-bit A/D converter with 8 analog input channels that draws 500 nanoamps running at 1K 6-bit samples/sec to 200 microamps running at 1M 12-bit samples/sec, a 4×40-segment LCD driver with built-in voltage booster that draws 900 nanoamps, a low-energy UART (a “LUART”) that draws 100 nanoamps running at 9600 bps, and a 32-KHz clock/counter that draws 50 nanoamps.

Energy Micro claims that the autonomous peripherals in the EFM32 microcontroller can chop a few more rectangles out of the energy-consumption curve, keeping the processor dormant longer, so that it can get 10 years out of that CR2032 coin-cell battery. That’s four times longer than the next competitive microcontroller, according to Energy Micro.

In addition to these autonomous peripherals there’s a DAC, a power-on reset circuit, real-time clock/counter, watchdog timer, power-monitor, etc. Oh yes, there’s 16 to 128Kbytes of Flash and 8 to 16 Kbytes of RAM on the chip along with the ARM Cortex-M3 processor core and the assorted peripherals. A large number of family members (22) with the usual mix-and-match combinations of peripherals and memory found in most microcontroller families are planned.

What might you do with such low-power devices? Energy Micro’s Web site lists a lot of interesting applications including energy and utility metering (electricity meters, water meters, gas meters, and heat cost allocators), home and building control (HVAC systems, lighting control, smart home systems), alarm and security systems (burglar alarms, fire and safety alarms, smoke detectors, surveillance systems), industrial automation (temperature sensors, pressure sensors, vibration sensors, motion sensors), medical devices (pacemakers and defibrillators, glucose meters, blood-pressure monitors), remote controls (IR and RF remote controls, keyless entry), identification systems (RFID, tracking systems, access control), sporting goods and equipment (GPS, sport watches, MP3 players, pulse and pace monitors), and climate monitoring (humidity sensors, CO2 and gas sensors, temperature sensors, and corrosion detectors). That list is hardly exhaustive, but it’s a darn good start.

The first EFM32 microcontroller chips are packaged in QFN64 and BGA112 packages, which are currently sampling with lead customers. Pricing starts at $1.55 in 100k quantities for 32-pin packages. Interested? Development kits are supposed to be available this month. Samples will be available next month in December. Volume deliveries are scheduled for February, 2010. www.energymicro.com.