Can the Magneticians finally succeed in getting MRAM launched as a viable, low-power ASIC NV memory?

One of the interesting technology efforts in evolving memory technology is the development of MRAM (magnetoresistive RAM), which is RAM based on a magnetic storage mechanism very similar to the magnetoresisitive mechanisms used in rotating magnetic storage including hard and magneto-optical disk drives. Back in the 1950s and 1960s, magnetic memory was all we had. It was called core memory and it was laboriously hand woven from wires and ferrite cores. It was expensive and increasingly slow compared to the processors it supported.

Semiconductor RAM obliterated core memory almost overnight when Intel introduced the 1-kbit 1103, the first commercially successful DRAM. The year was 1970. Within two years, Intel’s 1103 was the semiconductor industry’s top selling IC. Since then, magnetic memory has been a footnote in commercial processor-based designs. That could change soon, thanks to MRAM, but not without a lot of effort.

Many startup companies plus established memory IC vendors including IBM have invested heavily in developing magnetic RAM process technologies that are compatible with semiconductor manufacturing. The only company with commercial products so far appears to be Everspin Technologies, which was spun out of Freescale in 2008. Everspin’s Web site lists parts with capacities to 16 Mbits (that’s megabits, with an “M”). Of course, the big benefit of MRAM is that it’s nonvolatile. But so is NAND Flash memory, which is available in Gbit (gigabit, with a “G”) densities. So what does MRAM have to offer that Flash does not? “Fast, symmetrical read/write times” says Barry Hoberman, who is in charge of business development for MRAM startup Crocus Technology. Also, MRAM storage elements don’t wear out the way floating gates do in NAND Flash storage cells. Both types of memory can be considered low-power alternatives to memory storage because neither requires refresh cycles or power to retain stored information.

I met with Hoberman at this week’s GSA Emerging Opportunities Expo and Conference, held in the Santa Clara Convention Center. We discussed MRAM and a new type of MRAM that Crocus had just announced as a technology development. But first, a bit of MRAM review.

The conventional MRAM storage element is called a Magnetic Tunnel Junction (MTJ), which consists of a sandwich of one fixed and one switchable magnetic layer separated by a tunnel junction. Write currents can switch the magnetic orientation of the switchable layer and the resulting MTJ structure has a measurably different resistance depending on whether the magnetic polarities of the fixed and switchable layers are aligned or are opposed. The difference in resistance provides the readout of the cell’s state.

Crocus, an outgrowth of the CNRS and CEA national labs in Grenoble, France, also has an MRAM, based on what the company calls thermal-assisted switching (TAS), which raises the temperature of the MTJ during the write cycle to soften the cell’s hardness against magnetic polarity change. Once cooled, the cell regains its magnetic hardness. TAS reduces the required write currents, improves cell retention stability, and permits use of a single inductive write line. Crocus does not yet market the part TAS MRAM commercially but there are plans to put the Crocus TAS MRAM technology goes into production. However, says Hoberman, the approach won’t scale well below 65nm.

The reasons for this go to the heart of why MRAM has failed to catch on so far. First, the currents needed to switch an MTJ are not small. Magnetic switching in a non-TAS MRAM cell occurs where two energized wires intersect and when nearby conductors supply enough combined magnetic flux to switch the magnetic material’s polarity. This mechanism looks a lot like the one used for magnetic-core memory in the middle of the 20th century and requires a fair amount of current. TAS switching uses a one energized wire to supply swiching flux plus the heating of the MTJ, but the required switching current still doesn’t scale well. That’s a bad trend that impedes MRAM scalability.

Second, the stability-the “hardness” of the magnetic storage or the MTJ’s resistance to inadvertent thermally-induced switching-doesn’t seem to scale very well either, so moving to smaller geometries creates real storage-reliability problems as the parts are scaled to densities approaching that of today’s NAND Flash devices.

Make no mistake, NAND Flash memories also have storage-reliability problems as vendors strive to pack 2, 3, and 4 bits per cell using multilevel technologies, necessitating the increasingly heavy use of ECC as signal/noise ratios degrade. However, the onset of MRAM stability loss with shrinking cell size appears to be particularly fast, according to Hoberman, and you quickly go from needing no ECC to needing a lot of ECC bits. In our discussion, Hoberman mentioned 100% redundant memory arrays as an extreme case. That’s probably not acceptable to most designers and the trend does not bode well for existing MRAM technologies.

Hence Crocus’ recent announcement of developing a working prototype cell of a different sort of MRAM technology dubbed STT for “spin torque transfer.” This is clearly the technology Crocus intends to pursue as lithographies continue to shrink.

At this point, you should note that several companies are currently developing STT MRAMs although I discussed only Crocus’ STT technology with Hoberman. Also note: Crocus’ STT cell uses a different magnetic film configuration than the company’s existing TAS MTJ technology.

STT cells use a different write mechanism than earlier MRAM cells. A Crocus STT MRAM writes an MTJ cell by driving a write current directly through the MTJ instead of using magnetic flux emanating from adjacent, current-carrying wires to write a bit. First, the write current passes through one of the STT MTJ’s two permanently polarized magnetic layers. The majority of the electrons passing through this first permanently polarized layer become magnetically polarized by acquiring the same spin, as imposed by the magnetized layer. These electrons then impart this magnetic polarity to the switchable magnetic layer once they cross the tunnel junction and pass through the switchable layer. Reversing the voltage across the MTJ drives electrons first through a different permanently polarized layer that has an opposed magnetic orientation, imposing a reverse magnetic polarity in the switchable layer, again through electron-spin transfer. The switchable layer’s magnetic polarity is then sensed using a resistive readout.

Crocus employed 50nm lithography to create its new prototype STT MRAM cells, as opposed to the 90-130nm lithographic processes used to fabricate the company’s TAS MTJs. At 50nm, the STT MTJ is about the same size as the underlying switching transistor used to drive current through the MTJ, which bodes well for achieving high cell density.

The write current for Crocus’ prototype STT MTJ is 50 to 100 microamps and the read and write cycle times are less than 10 nsec. These are impressive numbers that will surely attract some attention from systems and ASIC designers. Significantly says Hoberman, the STT MTJ’s write current scales in the right direction, shrinking with the square of the linear lithographic dimension of the MTJ while storage stability remains good and will not change significantly. Hoberman also mentioned that Crocus has worked on building in the additional magnetic stability needed for a scalable STT MRAM cell. So Crocus’ STT MRAM technology appears to overcome many of the scalability limitations of earlier MRAM technologies and it also seems to open the path to the sorts of memory densities achieve by NOR Flash and that can start to approach the densities achieved by SLC NAND Flash devices.

None of this MRAM technology amounts to much if there’s no fab to build it. Technology without production is merely interesting and one of the biggest problems with many new memory technologies is that they introduce new materials into the manufacturing flow. Most foundries do not wish to do anything to disrupt their manufacturing flows. However, in June of this year, Tower Semiconductor and Crocus announced an agreement to port Crocus’ TAS MRAM process to Tower’s manufacturing environment. That agreement was for Crocus’ TAS MJT thin-film technology, but Hoberman claims that the magnetic thin film used for the STT technology is similar enough that it will readily transfer to Tower. Nevertheless, he says, Tower has not officially announced that it will port Crocus’ STT technology.

What this all means is that some time next year, system and ASIC design teams may be able to consider some form of Crocus MRAM as a viable choice for on-chip and board-level memory. Tower will be able to manufacture ASICs with on-chip, non-volatile MRAM using Crocus’ MRAM IP and Crocus will be offering stand-alone MRAM chips to board-level designers. Whether it will be the TAS technology, the STT technology, or both technologies remains to be seen.

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