Steve Leibson

What would you ask my panelists about Green Chip design?

I’m chairing a panel on Green Chip design at the 7th International SOC Conference next week. What would you ask the panelists about green ASIC/FPGA design if you were there? Here’s a list of panelists:

“Green Chips: Technology, Trends, and Challenges in Low-Power Multicore SoC Designs” (http://j.mp/1D0hfW)

1. Dr. Barry Pangrle, Solutions Architect, Low Power, Design and Verification, Mentor Graphics.

2. Dr. Sho Long Chen, President, CEO, Founder and Chairman, Vweb Corporation

3. Michel Laurence co-founded Octasic.

4. Jasbinder Bhoot, Vice President, Worldwide Marketing, eASIC Corporation.

5. Jauher Zaidi, CEO, PalmChip Corporation

6. Alan Ruberg, SPMT architect for SPMT, The Serial Port Memory Technology consortium.

What do Superman, ASIC and SOC Design, and Newport Beach have in common?

Hi.

• Do you design ASICs or SOCs?
• Do you work on a team that designs ASICs or SOCs?
• Do you manage a team that designs ASICs or SOCs?

Let me ask you a question then. What’s the one thing you will do from now to the end of the year that will put you or your team ahead of the rampant, cutthroat global competition it will face in 2010? Do you even know?

Let me give you the typical answer, the answer that I know I’d get from most of the engineers, designers, managers, and executives in this industry. It’s a one-word answer. I know it because I’ve heard this answer over and over again. That answer is… nothing.

What!?!?!

Absolutely, positively nothing.

The depressing reality of the SOC design industry is that it has been on cruise control for years. It’s been on incremental improvement for years while increasingly advanced silicon outstrips our ability to exploit it. Here are some of the things I’ve heard over and over again during this decade:

• Just give us tools that are a little better than last year’s.
• I just want to push a button and have all my work done for me.
• I don’t have time to read.
• I don’t go to DAC.
• I don’t go to any shows or conferences because my travel budget’s tight (or gone).

Sound familiar?

Well, you’ve got another chance. Early next month, the Seventh International SOC Conference takes place in Newport Beach. This hidden gem of a conference has been quietly going on under the noses of almost every SOC design team in the world for nearly the entire decade and chances are very good that your competitors have never gone to even one of these conferences. Heck, chances are good that you haven’t either.

Beyond the meeting room doors of this conference, a very few forward-looking people from the industry elite have spent the few bucks needed to drive or take a Southwest Airlines flight to the Orange County/Santa Ana/John Wayne airport, which is almost within walking distance of the inexpensive conference hotel. This is one SOC design conference where it’s easy to convince your boss that you’re not on a junket. One look at a photo of the hotel will be all it takes.

There’s not a design team on the planet right now that’s not frightened and confused, uncertain of what to do, worried, and struggling. What every one of them lack is insight. What they expect, I guess, is to somehow be struck with insight by divine inspiration.

It ain’t coming.

You want inspiration? You have to go out and get it. Aggressively.

In the high-stakes game of chip design, one idea is worth hundreds of thousands or millions of dollars if it saves you a week or a month of development time. Many millions of dollars if it saves you a respin. Many tens of millions of dollars if your team gets the design win and your competitors don’t.

Can YOU imagine getting that design win, recession be damned? If you can’t, doesn’t that suggest there’s something you don’t know? Something that someone else possibly does know? Something you need to know? Someone with that one idea may well be presenting at the Seventh International SOC Conference. Maybe it’s a new facet to low-power design. Maybe it lies at the intersection of silicon tech and biotech. Maybe it’s not in the head of someone on stage at all but in the head of that person sitting right next to you. Who knows?

One thing’s for sure. You won’t find out sitting in front of your PC’s screen yet another day. If you find it in there, your competition has found it too.

I read a lot of comic books when I was young. Perhaps you too are familiar with the origin legend of Superman. If so, you know he was sent to earth as a child, rushed off the planet Krypton in a one-man rocket, barely in time, before the entire planet exploded. His life saved by his father Jor-El. When he landed on earth, due to the difference in suns, gravity, and atmospheres, little Kal-El had gained superhuman powers.

He was, in fact, an alien from another planet in a distant galaxy.

The analogy is obvious. Our “planet” as we’ve known it (planet SOC) is literally in destruction, endangered by economic forces beyond the control of your design team or anyone else’s. Continuing as you have guarantees pain and suffering. OR YOU CAN CHOOSE TO ROCKET TO A DIFFERENT PLANET IN A DIFFERENT UNIVERSE NOW. Actually, all it really takes is a flight or drive to Newport Beach in Southern California.

It’s your choice. I dare you to click here.

PS: Either way, it doesn’t matter to me. I’ve no financial interest in this conference. Just an interest in seeing this industry move forward.

A Field-Programmable Power System IC

Years ago, systems designers had it relatively easy with respect to system power supplies. Logic ran on 5V power; hard and floppy disk drives needed an additional 12V supply; and the rest of the system would operate off of those two supply voltages plus perhaps one more negative voltage supply. The expanded requirements of today’s complex systems demand power subsystems with far more abilities than ever before. In addition to the need for many more supply voltages, more efficient power regulation, power and reset sequencing, and drift insensitivity, today’s complex, low-power system designs need far more precise and programmable control over the supply voltages. The reasons for these additional requirements can be seen in the advanced chips-such as FPGAs, media processors, SOCs, and ASSPs-that lie at the heart of today’s systems. For example, the most advanced FPGAs require three or four supply voltages to help minimize power consumption.

All of today’s complex logic devices (FPGAs, ASICs, SOCs, ASSPs, etc.) have far more complex power requirements. Just one such chip in a system, like the FPGA example above, may need three or four supply voltages. The order and timing in which these multiple supply voltages come up can also be critical to successful system initialization. The order in which these voltages switch off during power-down operations may also be critically important to proper chip shutdown and can also be critical to preventing supply-induced damage to the IC. The timing relationship between a reset line or multiple reset lines and the supply voltages can be quite important as well.

What’s now required is a field-programmable power supply or system (FPPS) that can provide multiple finely programmable supply voltages with independently adjustable ramp-up and ramp-down times and adjustable sequencing delays between the various supply voltages. Such a power subsystem design provides the system designer with the needed design flexibility. The reason such systems are not widely used today is because they have been prohibitively expensive. It’s not that the required foundation technology itself is prohibitively expensive; it’s because power-IC vendors previously had not applied sufficient levels of silicon integration to the design problem. However, that situation was bound to change…and it has.

The newly introduced XRP7704 and XRP 7740 FPPS controller ICs from Exar incorporate all of the functions required to implement a 5-output FPPS. The chips contain four programmable switching voltage controllers with integrated FET drivers that can drive external high- and low-side power MOSFETs to create efficient switching power supplies with current capacities of 5A to 16A per channel for the XRP7704 and XRP7740 respectively. Power MOSFETs and a few additional passive devices are all that’s needed to implement four high-current, switching power sources operating at four different programmable supply voltages. The XRP7704 and XRP7740 also contain a configurable linear, 100mA, low-dropout (LDO) voltage regulator that can supply a fifth system supply voltage (3.3 or 5V). The configurable LDO regulator can be used as a keep-alive power supply for system components that must remain powered up while the rest of the system is powered down.

In addition to the programmable supply voltages, the XRP7704 and XRP7740 can automatically control the power-up and power-down characteristics of the voltage supplies through programmable preset parameters. These FPPS chips can independently control the ramping speed for each of the four voltage channels and they can control the relative timing between the supply voltages. This last characteristic allows the system designer to bring up some supply voltages before others, as required by many complex logic ICs including FPGAs, media processors, ASICs, SOCs, and ASSPs.

The XRP7704 and XRP7740 also incorporate several system-management functions related to the power supply including under-voltage and power-good monitoring, over-temperature operation and fault handling. All of these system monitors are configurable as well and their status can be queried by a host processor via the chip’s I2C interface.

Samples of the XRP7704 are available now and are priced at $4.00 in 1K quantities. Samples of the XRP7740 will be available by the end of October. The XRP7740 is priced at $5.50 in 1K quantities. Additional information can be found at www.exar.com.

(Note: This blog entry is based on a White Paper that I have written for Exar on FPPS controller chips.)

Give OTP a chance for low-power, on-chip storage

The on-chip memories that get most of the attention are read/write memories such as SRAM, DRAM, Flash, and MRAM (which I just covered in my previous blog entry). However, there’s a place for OTP (one-time programmable) memory on chip, so the technology bears some thought. I discussed OTP at last week’s GSA Emerging Opportunities Expo and Conference in Santa Clara, California with Jim Lipman of Sidense, a vendor that offers hard IP for on-chip OTP memory.

Sidense’s SiPROM memory cell consists of one specially designed FET as shown in the figure below. The special part of the FET’s design is a stepped gate-oxide layer with two thicknesses: thick and thin. Unprogrammed, the FET looks like a FET. Programming causes a controlled disruption in the thin part of the FET’s channel-oxide insulation to produce a conduction path from the FET’s gate to the conduction channel. Charge-coupled sense amps can detect whether or not an FET in the OTP array has or has not been programmed.

It’s because of the charge-coupled sense amps that Sidense’s SiPROM technology qualifies as a low-power memory technology. These sense amps are only on for tens of nanoseconds during a read cycle and are not powered continuously. This is a patented feature of Sidense’s technology.

Although designers have an obvious bias towards read/write technologies for on-chip memory, OTP memory can be quite useful for storing infrequently programmed or reprogrammed data such as calibration and trim settings, serial numbers, configurations, boot code, and security keys. This last application is particularly interesting. Lipman provided an example. The security keys for the HDMI digital display interface spec need about 2.5 kbits for storage. However, there’s the possibility that the security can be broken and that new keys will need to be distributed. A 16-kbit array of OTP memory can store about six sets of HDMI keys, which should be enough storage to last beyond the expected life of the end equipment.

You should also be aware of the factors that argue in favor of on-chip OTP memory. Sidense’s cells are about 1.2x larger than ROM cells, so there’s a 20% size penalty in exchange for the flexibility of programmability. In exchange for this size penalty, there’s no need for a mask change if the data stored in the OTP ROM needs to be changed in the factory or in the field (for an update).

In addition, Sidense’s OTP memory easily tracks IC manufacturing process changes although it’s hard IP, so Sidense must tailor the IP for each vendor’s process technology. Sidense’s SiPROM products are currently available from 180nm to 55nm and are portable to 40nm and below. Supported foundries include TSMC, UMC, Fujitsu Microelectronics, SMIC, Tower, IBM and Chartered.

It’s also interesting to compare OTP memory with Flash. Lipman says that Sidense’s OTP SiPROM cells are about half the size of Flash cells for a given semiconductor technology. In addition, the creation of Flash-cell floating gates adds process changes that can add roughly 30% to wafer production costs. Finally, Flash process technology is clearly getting into trouble as lithographies shrink. Some presenters at the recent Flash Memory Summit were predicting that the 22nm node might be the last node to support Flash memory, although such end-of-the-world prognostications from the semiconductor pundits are often wrong. By contrast, Sidense’s SiPROM cells require only standard CMOS processing, so the company claims it’s easier for their OTP memory than it is for Flash cells to track process improvements.

Can the Magneticians finally succeed in getting MRAM launched as a viable, low-power ASIC NV memory?

One of the interesting technology efforts in evolving memory technology is the development of MRAM (magnetoresistive RAM), which is RAM based on a magnetic storage mechanism very similar to the magnetoresisitive mechanisms used in rotating magnetic storage including hard and magneto-optical disk drives. Back in the 1950s and 1960s, magnetic memory was all we had. It was called core memory and it was laboriously hand woven from wires and ferrite cores. It was expensive and increasingly slow compared to the processors it supported.

Semiconductor RAM obliterated core memory almost overnight when Intel introduced the 1-kbit 1103, the first commercially successful DRAM. The year was 1970. Within two years, Intel’s 1103 was the semiconductor industry’s top selling IC. Since then, magnetic memory has been a footnote in commercial processor-based designs. That could change soon, thanks to MRAM, but not without a lot of effort.

Many startup companies plus established memory IC vendors including IBM have invested heavily in developing magnetic RAM process technologies that are compatible with semiconductor manufacturing. The only company with commercial products so far appears to be Everspin Technologies, which was spun out of Freescale in 2008. Everspin’s Web site lists parts with capacities to 16 Mbits (that’s megabits, with an “M”). Of course, the big benefit of MRAM is that it’s nonvolatile. But so is NAND Flash memory, which is available in Gbit (gigabit, with a “G”) densities. So what does MRAM have to offer that Flash does not? “Fast, symmetrical read/write times” says Barry Hoberman, who is in charge of business development for MRAM startup Crocus Technology. Also, MRAM storage elements don’t wear out the way floating gates do in NAND Flash storage cells. Both types of memory can be considered low-power alternatives to memory storage because neither requires refresh cycles or power to retain stored information.

I met with Hoberman at this week’s GSA Emerging Opportunities Expo and Conference, held in the Santa Clara Convention Center. We discussed MRAM and a new type of MRAM that Crocus had just announced as a technology development. But first, a bit of MRAM review.

The conventional MRAM storage element is called a Magnetic Tunnel Junction (MTJ), which consists of a sandwich of one fixed and one switchable magnetic layer separated by a tunnel junction. Write currents can switch the magnetic orientation of the switchable layer and the resulting MTJ structure has a measurably different resistance depending on whether the magnetic polarities of the fixed and switchable layers are aligned or are opposed. The difference in resistance provides the readout of the cell’s state.

Crocus, an outgrowth of the CNRS and CEA national labs in Grenoble, France, also has an MRAM, based on what the company calls thermal-assisted switching (TAS), which raises the temperature of the MTJ during the write cycle to soften the cell’s hardness against magnetic polarity change. Once cooled, the cell regains its magnetic hardness. TAS reduces the required write currents, improves cell retention stability, and permits use of a single inductive write line. Crocus does not yet market the part TAS MRAM commercially but there are plans to put the Crocus TAS MRAM technology goes into production. However, says Hoberman, the approach won’t scale well below 65nm.

The reasons for this go to the heart of why MRAM has failed to catch on so far. First, the currents needed to switch an MTJ are not small. Magnetic switching in a non-TAS MRAM cell occurs where two energized wires intersect and when nearby conductors supply enough combined magnetic flux to switch the magnetic material’s polarity. This mechanism looks a lot like the one used for magnetic-core memory in the middle of the 20^th century and requires a fair amount of current. TAS switching uses a one energized wire to supply swiching flux plus the heating of the MTJ, but the required switching current still doesn’t scale well. That’s a bad trend that impedes MRAM scalability.

Second, the stability-the “hardness” of the magnetic storage or the MTJ’s resistance to inadvertent thermally-induced switching-doesn’t seem to scale very well either, so moving to smaller geometries creates real storage-reliability problems as the parts are scaled to densities approaching that of today’s NAND Flash devices.

Make no mistake, NAND Flash memories also have storage-reliability problems as vendors strive to pack 2, 3, and 4 bits per cell using multilevel technologies, necessitating the increasingly heavy use of ECC as signal/noise ratios degrade. However, the onset of MRAM stability loss with shrinking cell size appears to be particularly fast, according to Hoberman, and you quickly go from needing no ECC to needing a lot of ECC bits. In our discussion, Hoberman mentioned 100% redundant memory arrays as an extreme case. That’s probably not acceptable to most designers and the trend does not bode well for existing MRAM technologies.

Hence Crocus’ recent announcement of developing a working prototype cell of a different sort of MRAM technology dubbed STT for “spin torque transfer.” This is clearly the technology Crocus intends to pursue as lithographies continue to shrink.

At this point, you should note that several companies are currently developing STT MRAMs although I discussed only Crocus’ STT technology with Hoberman. Also note: Crocus’ STT cell uses a different magnetic film configuration than the company’s existing TAS MTJ technology.

STT cells use a different write mechanism than earlier MRAM cells. A Crocus STT MRAM writes an MTJ cell by driving a write current directly through the MTJ instead of using magnetic flux emanating from adjacent, current-carrying wires to write a bit. First, the write current passes through one of the STT MTJ’s two permanently polarized magnetic layers. The majority of the electrons passing through this first permanently polarized layer become magnetically polarized by acquiring the same spin, as imposed by the magnetized layer. These electrons then impart this magnetic polarity to the switchable magnetic layer once they cross the tunnel junction and pass through the switchable layer. Reversing the voltage across the MTJ drives electrons first through a different permanently polarized layer that has an opposed magnetic orientation, imposing a reverse magnetic polarity in the switchable layer, again through electron-spin transfer. The switchable layer’s magnetic polarity is then sensed using a resistive readout.

Crocus employed 50nm lithography to create its new prototype STT MRAM cells, as opposed to the 90-130nm lithographic processes used to fabricate the company’s TAS MTJs. At 50nm, the STT MTJ is about the same size as the underlying switching transistor used to drive current through the MTJ, which bodes well for achieving high cell density.

The write current for Crocus’ prototype STT MTJ is 50 to 100 microamps and the read and write cycle times are less than 10 nsec. These are impressive numbers that will surely attract some attention from systems and ASIC designers. Significantly says Hoberman, the STT MTJ’s write current scales in the right direction, shrinking with the square of the linear lithographic dimension of the MTJ while storage stability remains good and will not change significantly. Hoberman also mentioned that Crocus has worked on building in the additional magnetic stability needed for a scalable STT MRAM cell. So Crocus’ STT MRAM technology appears to overcome many of the scalability limitations of earlier MRAM technologies and it also seems to open the path to the sorts of memory densities achieve by NOR Flash and that can start to approach the densities achieved by SLC NAND Flash devices.

None of this MRAM technology amounts to much if there’s no fab to build it. Technology without production is merely interesting and one of the biggest problems with many new memory technologies is that they introduce new materials into the manufacturing flow. Most foundries do not wish to do anything to disrupt their manufacturing flows. However, in June of this year, Tower Semiconductor and Crocus announced an agreement to port Crocus’ TAS MRAM process to Tower’s manufacturing environment. That agreement was for Crocus’ TAS MJT thin-film technology, but Hoberman claims that the magnetic thin film used for the STT technology is similar enough that it will readily transfer to Tower. Nevertheless, he says, Tower has not officially announced that it will port Crocus’ STT technology.

What this all means is that some time next year, system and ASIC design teams may be able to consider some form of Crocus MRAM as a viable choice for on-chip and board-level memory. Tower will be able to manufacture ASICs with on-chip, non-volatile MRAM using Crocus’ MRAM IP and Crocus will be offering stand-alone MRAM chips to board-level designers. Whether it will be the TAS technology, the STT technology, or both technologies remains to be seen.

Drop-in Synopsys’ DesignWare minPower IP components and cut ASIC power

Last week, I listened to a Webinar by Synopsys’ Jay Chiang on the DesignWare minPower IP components that the company introduced at this year’s DAC. Chiang did an excellent job and made a compelling case for using these IP components. Bottom line: some early users of DesignWare minPower IP components report as much as a 48% power savings at the block level and as much as a 24% power savings at the chip level. Those reported results should be significant enough to make every ASIC/SOC design team sit up and take notice although be cautioned, your mileage may vary (YMMV). (An archived version of the Webinar can be viewed here.)

DesignWare minPower IP components complement and do not replace existing low-power design techniques such as clock gating and the use of multi-Vt transistors. These IP components also work with more advanced low-power design approaches such as multi-voltage islands, MTCMOS (multi-threshold CMOS) logic, multi-voltage with power gating, and DVFS (dynamic voltage and frequency scaling) techniques. The minPower IP approach introduces new IP blocks at the logical design level, just after functional design and just before physicla layout. You add these new IP components by simply adding the new minPower IP database before logic synthesis.

One of the most effective ways to save power in a design is to determine the design’s functional operating modes and then to turn off whatever’s not needed in each mode. Using this approach, you can turn off the clocks to the unused blocks to cut dynamic power and you can also gate the power to these blocks, which cuts both dynamic and static power. However, you usually cannot turn off everything in a design. Something must remain awake so that the appropriate functions can be awakened at the proper time. For example, you cannot turn off the receiver in a mobile phone handset or you’ll miss incoming calls. For those blocks that cannot be shut down, you need other power-saving design approaches.

That’s where the Synopsys DesignWare minPower IP components come into play. They provide low-power logic structures that derive their low-power characteristics from one or more of three design approaches:

• Low-power datapath architectures. These datapaths are specifically designed to reduce glitches and to prevent glitches from propagating. They are also designed to minimize switching activity.
• Power- and switching-aware datapath structures. The use of these structures is based on power criteria when the synthesis tool can infer switching activity and power consumption.
• Instantiated low-power IP based on data tracking, enhanced clock gating, and data-specific datapath gating.

The DesignWare minPower datapath structures are designed to be balanced and shallow to minimize switching activity. They’re also designed to generate fewer glitches and to prevent glitch propagation. Synthesis of these datapaths also focuses on generating less switching activity by exploiting the presence of low-activity bits based on the distribution of data values moving through the pipeline. Consequently, datapath encoding is based on an analysis of operand activity through the pipeline. There’s also some amount of optimization based on variable data slack through the pipeline. Different signals propagate through a pipeline at different speeds and the DesignWare minPower IP blocks can be modified to exploit available differential slack within the pipeline to reduce power consumption.

The synthesis tool will also look for ways to reduce the number of pipeline stages that high-activity signals must propagate through and will swap the inputs on two operands entering into a function if doing so reduces power consumption. All of this evaluation would seem to require substantial amounts of simulation to evaluate the data-specific results of power optimization.

The power-aware structures in the DesignWare minPower IP collection are designed for the optimization of delay first (you still must meet timing goals), followed by power consumption and then area. Thus you might actually see some area increase with this approach if it produces substantial power savings and indeed, some of the results shown in this Webinar indicated an area increase of a few percent.

There are three IP categories within the DesignWare minPower IP line:

• Data-tracking pipelines (patented by Synopsys)
• Enhanced clock gating
• Datapath logic with built-in gating

The data-tracking pipelines are designed to suppress data bubbles within the pipeline that contain invalid data (indeterminate, glitchy data), which reduces the extraneous switching activity caused by this sort of data. These structures alone reduce power consumption on the order of 20%. That’s pretty significant. The enhanced clock gating takes the amount of clock gating in specific IP blocks from about 60% to more than 90%, which can also result in a power savings on the order of 20%. Still significant.

Even better results come from merging clock-gating logic with the datapath’s computational logic-treating the clock gating as just part of the datapath’s logic and optimizing the whole ball of wax. Power savings on the order of 30% can result.

More significant than all of the above however, is that this design approach is the Holy Grail that designers seek: a drop-in tool that requires that designers learn next to nothing while saving substantial amounts of power. Because it appears at first glance that Synopsys’ DesignWare minPower IP is just such a drop-in tool, it’s sure to get a good, close look by design teams questing for the Holy Grail of design tools.