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Monthly Archives: October 2009
What would you ask my panelists about Green Chip design?
I’m chairing a panel on Green Chip design at the 7th International SOC Conference next week. What would you ask the panelists about green ASIC/FPGA design if you were there? Here’s a list of panelists: “Green Chips: Technology, Trends, and … Continue reading
Posted in Design, Green Design, Low-Power
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What do Superman, ASIC and SOC Design, and Newport Beach have in common?
Hi. Do you design ASICs or SOCs? Do you work on a team that designs ASICs or SOCs? Do you manage a team that designs ASICs or SOCs? Let me ask you a question then. What’s the one thing you … Continue reading
Posted in Design, EDA, ESL, Low-Power
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A Field-Programmable Power System IC
Years ago, systems designers had it relatively easy with respect to system power supplies. Logic ran on 5V power; hard and floppy disk drives needed an additional 12V supply; and the rest of the system would operate off of those … Continue reading
Give OTP a chance for low-power, on-chip storage
The on-chip memories that get most of the attention are read/write memories such as SRAM, DRAM, Flash, and MRAM (which I just covered in my previous blog entry). However, there’s a place for OTP (one-time programmable) memory on chip, so … Continue reading
Can the Magneticians finally succeed in getting MRAM launched as a viable, low-power ASIC NV memory?
One of the interesting technology efforts in evolving memory technology is the development of MRAM (magnetoresistive RAM), which is RAM based on a magnetic storage mechanism very similar to the magnetoresisitive mechanisms used in rotating magnetic storage including hard and … Continue reading
Drop-in Synopsys’ DesignWare minPower IP components and cut ASIC power
Last week, I listened to a Webinar by Synopsys’ Jay Chiang on the DesignWare minPower IP components that the company introduced at this year’s DAC. Chiang did an excellent job and made a compelling case for using these IP components. … Continue reading