Monthly Archives: September 2009

TI Low-Power RF Workshop Covers Four RF Networking Protocols

Texas Instruments is conducting two low-power RF-networking workshops in the immediate future and if you’re working on anything connected with low power, RF, and networking, you might want to consider signing up. There is a 2-day workshop and a 4-day … Continue reading

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Use Sleep Mode for All It’s Worth to Cut Power Consumption

One way to cut power and energy consumption in processor-based systems is to put the processor to sleep. No work gets done when the processor is asleep so you need to wake it up once in a while so it … Continue reading

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Could A Low-Power Middle Ground Between ASICs/SOCs and FPGAs Help You?

You can’t always get what you want, But if you try sometime, You’ll find, You get what you need. Those lyrics from a song from the Rolling Stones describes the situation with ASICs/SOCs and FPGAs. For low power, you want … Continue reading

Posted in CMOS, Design, EDA, Low-Power | Tagged , , , | 1 Comment

FPGAs as ASSP/Microcontroller Helpers – When ASICs and SOCs Won’t Do

Without doubt, an ASIC or SOC is the way to create systems with the lowest power dissipation. However, many other factors can mitigate the advantages of custom system silicon. Those factors include a critical and looming market window, a lack … Continue reading

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