Squeezing Excess Power Out of Synthesized Blocks

With the glacial-like industry move towards transaction-level simulation using OSCI’s TLM 2.0, I think that C and SystemC will be used more and more for the initial descriptions of large portions of many systems. Many system blocks will therefore end up as compiled software (or firmware) running on standard-architecture processors and application-specific processors because it’s just easier to compile such descriptions and run them on processors. C and SystemC are sequential languages and they just beg to be implemented as firmware running on a processor.

But processors just aren’t the right implementation solution for every design problem. Sometimes, it just has to be gates; Lots of them. There are two ways to generate gate-level designs. One way is to write an RTL description of the block by hand and then verify it through simulation. I discussed a way to fit such a block into a system-level simulation using Mentor’s Vista in a previous blog entry. Mentor’s Vista incorporates a model builder that will generate a TLM 2.0 functional description of an RTL block. Another way to generate gate-level block designs from a C or SystemC description is to synthesize the description and produce an RTL description.

Whether manually produced or synthesized, there’s a good chance that the resulting block will need some attention to squeeze excess power dissipation out of the design. Why? Because designers creating RTL descriptions often do not have the time to go back and make sure that all of a block’s clocks are gated off whenever possible and C or SystemC descriptions mostly omit any hints as to what portions of a block can be switched off during block operation, giving synthesis tools little to go on.

Enter Calypto and its SLEC (sequential logic equivalence checker) technology. I had an interesting discussion about SLEC and derivative products at DAC with Venkatram Krishnaswamy, Calypto’s VP of Applications Engineering and Solutions. The original idea behind SLEC was to formally verify equivalence between two block descriptions. Today, these block descriptions can be written in C, C++, SystemC, or RTL and SLEC can compare the blocks for equivalency. The original intent for creating SLEC was to find bugs but the resulting deep circuit analysis is useful for other tasks, like power reduction. The detailed sequential analysis technology developed for Calypto’s SLEC can deduce facts about that design that can help cut operating power.

SLEC can look at RTL blocks synthesized from C or SystemC and verify that a synthesized block is functionally equivalent to the original description. This is an important aspect of the product because C and SystemC descriptions are essentially untimed and therefore give synthesis tools many problems. Many C coders write C and SystemC code that’s not easily synthesized. Let’s face facts. It’s almost too easy to write hard-to-synthesize code in a language not originally intended to be synthesized. Calypto’s SLEC can detect the presence of synthesis impediments in the generated RTL and can help coders rewrite their source code with more detailed functional descriptions that help a synthesis tool generate better RTL. Think of SLEC as a second pair of mechanical eyes on the code that helps the code writer iterate on a C model that results in a better QOR (quality of results).

Detailed sequential analysis can deduce facts about that design that can help cut operating power and so Calypto has produced two additional tools based on sequential analysis that provide push-button power reduction for RTL blocks. The first such tool is called PowerPro CG, which inserts clock-gating enable logic into the RTL description based on an analysis of the RTL block’s sequential operation. This added RTL allows the logic-synthesis tool to more easily infer the required combinational clock gating. Gating clocks in sequential circuits cuts a block’s dynamic power consumption while raising static power consumption slightly due to increased gate count so there’s a balance to be struck. Of course a good block designer with sufficient time can analyze the block’s function and insert the clock-gating circuits manually. But who has the time? Typically, you find extensive clock gating only in highly leveraged blocks such as commercial processor IP cores.

Often, you need test vectors that exercise a block to ensure that you’ve caught all of the clock-gating opportunities. Although PowerPro CG isn’t perfect, Krishnaswamy estimated that PowerPro CG can find roughly 80% of the clock-gating opportunities without test vectors. If true, you know that most engineers will push the button and just take the 80%. Even though they might get most of the remaining 20% by writing a comprehensive test vector suite, well, “Who has the time?”

The other Calypto power-reduction tool is called PowerPro MG. It gates memories using similar analysis techniques. PowerPro MG exploits a “light-sleep” mode available in many of the latest static-memory IP cores available from vendors such as Virage Logic. The light-sleep mode, which is activated by a pin on the memory core, powers down the memory but retains memory state. PowerPro MG can take sleep and wake-up memory timing into consideration when determining the opportunities for exploiting light-sleep modes. Casual analysis of memory usage on SOCs will demonstrate that many memories are never put into a sleep mode, so there is much opportunity for power savings in this arena.

This entry was posted in Design, EDA, Low-Power. Bookmark the permalink.

One Response to Squeezing Excess Power Out of Synthesized Blocks

  1. Pingback: SKMurphy » DAC 2009 Blog Coverage Roundup

Leave a Reply