System-level design provides maximum control over power

Yesterday morning at DAC, Mentor Graphics rolled out a system-design tool called Vista (I guess Microsoft isn’t using that name any more). Mentor’s Vista is based on the OSCI TML 2.0 transaction-level modeling standard, which Mentor has adopted as a simulation platform. Mentor’s Vista allows system designers to perform design-space exploration and power analysis and it allows the software-development team to run and debug code on a virtual prototype.

The power-simulation features of Mentor’s Vista are critically important because system architects have the biggest knobs when it comes to dialing in system power. That may seem counterintuitive to you because we’ve been relying on circuit-design tricks and IC process-technology improvements to deliver the bulk of the reductions in system power for years. However, as the following bar chart shows, the really large reductions are available at the highest level, the architectural level.

It’s at this level that the design team makes critical decisions about how to allocate tasks—whether to firmware running on processors or to direct-execution hardware engines. These decisions directly affect system clock rates and therefore operating power. It’s also at this level that the software team can make tweaks to the system software that also have a huge impact on operating power. Algorithm selection does affect power dissipation, although many software-development teams may not be aware of the link between algorithm and power.

The key to making high-level TLM models work in a power-predictive way is to include power estimates in the same model with the functional description of the transaction-level model. Mentor’s Vista packages a transaction-based power model, a functional model, and a timing model into one TLM model package so that simulations can use one, two, or all three model components during a simulation. Of course, the simulation speed varies depending on how many of the model components are active during a simulation. The following image shows how the models are packaged in a Vista TLM model.

Vista can use functional models that are hand-written in SystemC. Vista also incorporates a model builder that can read an RTL model and produce a TLM functional model. This is really a key feature for Mentor’s Vista because most designers are currently not running system-level simulations due to lack of models. The model builder in Mentor’s Vista is a way to create those needed models.

Using TLM models for power analysis results in power simulations that run an estimated 100x to 1000x faster than power simulations that use RTL or gate-level simulations. Of course, the power-consumption results of TLM simulations are only as good as the power estimates for each transaction but the same can be said for RTL and gate-level simulations, which are also based on estimates.

The big advantage of TLM-based power simulations is the simulation speed. If architectural-level design is really the doorway to control over system power, then fast simulation is the key to that door because it provides a way to rapidly explore the available design space in a way never before possible.

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