Monthly Archives: July 2009

System-level design provides maximum control over power

Yesterday morning at DAC, Mentor Graphics rolled out a system-design tool called Vista (I guess Microsoft isn’t using that name any more). Mentor’s Vista is based on the OSCI TML 2.0 transaction-level modeling standard, which Mentor has adopted as a … Continue reading

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Free Pass to DAC Exhibits, All Week Long

Are you an EDA user with a hankering to attend DAC in a couple of weeks but don’t have the dough-re-mi and your company won’t spring for such a “frill” this year? Recently laid off as an EDA user? Denali, … Continue reading

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DAC’s Free Monday Returns to San Francisco. Apply Now. DAC’s in Three Weeks.

John Cooley’s DeepChip email this morning reports that EDAC, the consortium of EDA vendors, has decided to underwrite the long-time tradition of Free Monday at DAC which is coming up on July 27-less than three weeks from now. DAC’s at … Continue reading

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A Hunka, Hunka Burning CMOS (All About Latchup)

You’re a mere 10 minutes from completely understanding and preventing CMOS latchup in your low-power designs. Wizard of Oz Dave Jones has just posted his sixteenth EE Video Blog on these topics. Here it is:      

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