Steve Leibson

System-level design provides maximum control over power

Yesterday morning at DAC, Mentor Graphics rolled out a system-design tool called Vista (I guess Microsoft isn’t using that name any more). Mentor’s Vista is based on the OSCI TML 2.0 transaction-level modeling standard, which Mentor has adopted as a simulation platform. Mentor’s Vista allows system designers to perform design-space exploration and power analysis and it allows the software-development team to run and debug code on a virtual prototype.

The power-simulation features of Mentor’s Vista are critically important because system architects have the biggest knobs when it comes to dialing in system power. That may seem counterintuitive to you because we’ve been relying on circuit-design tricks and IC process-technology improvements to deliver the bulk of the reductions in system power for years. However, as the following bar chart shows, the really large reductions are available at the highest level, the architectural level.

It’s at this level that the design team makes critical decisions about how to allocate tasks—whether to firmware running on processors or to direct-execution hardware engines. These decisions directly affect system clock rates and therefore operating power. It’s also at this level that the software team can make tweaks to the system software that also have a huge impact on operating power. Algorithm selection does affect power dissipation, although many software-development teams may not be aware of the link between algorithm and power.

The key to making high-level TLM models work in a power-predictive way is to include power estimates in the same model with the functional description of the transaction-level model. Mentor’s Vista packages a transaction-based power model, a functional model, and a timing model into one TLM model package so that simulations can use one, two, or all three model components during a simulation. Of course, the simulation speed varies depending on how many of the model components are active during a simulation. The following image shows how the models are packaged in a Vista TLM model.

Vista can use functional models that are hand-written in SystemC. Vista also incorporates a model builder that can read an RTL model and produce a TLM functional model. This is really a key feature for Mentor’s Vista because most designers are currently not running system-level simulations due to lack of models. The model builder in Mentor’s Vista is a way to create those needed models.

Using TLM models for power analysis results in power simulations that run an estimated 100x to 1000x faster than power simulations that use RTL or gate-level simulations. Of course, the power-consumption results of TLM simulations are only as good as the power estimates for each transaction but the same can be said for RTL and gate-level simulations, which are also based on estimates.

The big advantage of TLM-based power simulations is the simulation speed. If architectural-level design is really the doorway to control over system power, then fast simulation is the key to that door because it provides a way to rapidly explore the available design space in a way never before possible.

Free Pass to DAC Exhibits, All Week Long

Are you an EDA user with a hankering to attend DAC in a couple of weeks but don’t have the dough-re-mi and your company won’t spring for such a “frill” this year? Recently laid off as an EDA user? Denali, Atrenta, and Springsoft want to make you an offer you can’t refuse: a full-week’s pass to DAC exhibits in exchange for a bit of information from you. Only for the first 600 people though, so better sign up quickly. Like right now! Where? Here.

DAC’s Free Monday Returns to San Francisco. Apply Now. DAC’s in Three Weeks.

John Cooley’s DeepChip email this morning reports that EDAC, the consortium of EDA vendors, has decided to underwrite the long-time tradition of Free Monday at DAC which is coming up on July 27-less than three weeks from now. DAC’s at San Francisco’s Moscone Center this year, so it’s accessible to all of Silicon Valley with a short car, bus, or train ride.

If you want to take advantage of “Free Monday” DAC registration, go to http://www.deepchip.com/FreeMonday.html. Complete all four registration pages. On the third page of the online registration form, you’ll find a newly added “Free Monday Exhibits” option. You must check this box to get free registration for Monday. The fourth page of the form will show a web receipt with their unique bar-code confirmation on it. You must print this entire page and bring it to DAC on Monday, July 27, where you’ll present the bar-code page to the Advance Registration desk located in Moscone Center’s North Lobby.

Coincidentally, I’m on a Pavilion Panel at 1 pm on what’s now Free Monday at DAC. I’m joining EDA luminary Jim Hogan, Stanford’s Per Enge, and Sonics’ Grant Pierce. We’re discussing the long road to system-level signoff. Hope to see you there because there’s no better way to wring power out of a system design than at the architectural level. Meanwhile, here’s an excerpt from a system-level design manifesto written by Hogan and Peter Levin:

“…we’re stubbornly bullish on the idea that abstraction is always, with no exception, the key to utility and productivity.  Because of the tremendous advances in – and therefore commoditization of – semiconductor manufacturing the value of complex devices, especially SoCs, is utterly dependent upon the ability to specify well, implement quickly, test for fidelity, and validate for function.  Of course, like the engine under the hood of a car, hardware matters; it can add to or detract from the user experience.  On the other hand, how many of us know or care about the brand of the motor. Most drivers take such things for granted, as long as their propulsion needs – expressed in (high level) terms of fuel economy, power and performance – are well satisfied. It is no accident that SoC design feels very similar to systems design, especially as software content becomes the primary factor of differentiation and scalability.

But don’t expect the polygon pushers to reach high into the system any more than you would expect an assembly programmer to build the advanced apps in a smart phone. Too expensive, too slow, too restrictive. When the wise men come, they will know two things:  how to integrate the components of design implementation in a way that obfuscates the details, and how to use abstraction to their benefit.  And they won’t call it ESL; however they may call it virtualization, just as they do today in the IT industry.

In fact, our customers are already years ahead of the tools they buy.  Sure, they care about compactness, manufacturability, and power.  But the real battleground – at least between them – is the truly differentiated trade-space between device integrity (does it do what I want it to do?), reliability (will it perform well, long, and under duress?), and security (am I assured of my privacy, and protection against nefarious intrusion?).

The promise of ‘system level’ anything – we’re going to propose a more ambitious new name in a second – is to break down the parochial boundaries that separate abstraction layers like so much cruddy varnish, and instead integrate them under in a common methodology and view.  This hypothetical tool – none exists yet but we’re unshakably optimistic – would truly facilitate architectural exploration without the constraining ties to hardware targets, bastardized (or proprietary) language, and prohibitive cost of migrating from simulation to emulation, and emulation to target platform.  Moreover, and crucially, it has to conveniently and sensibly accommodate the application software that differentiates our customers’ products in the market.  With possibly one large exception, this is basically how they make their profits.  In other words, it is a pre-requisite, and a recipe, for the holy grail of scale.”

A Hunka, Hunka Burning CMOS (All About Latchup)

You’re a mere 10 minutes from completely understanding and preventing CMOS latchup in your low-power designs. Wizard of Oz Dave Jones has just posted his sixteenth EE Video Blog on these topics. Here it is: