The Parallel Flow to Implementation: Verification
This issue of DACeZine is dedicated to razzle, dazzle implementation and physical design, otherwise known as the standard RTL to GDSII flow. Let’s not overlook the parallel flow –– verification, the most time-consuming and expensive part of hardware design. And did I mention, the most frustrating?
By consensus within the electronics industry and designers worldwide, verification consumes 70 percent or more of the development cycle. Digital media, telecommunications and mobile communications designs require massive amounts of verification to move meaningful data in and out of them. As we hit smaller process technologies, multicore architectures and increased reliance on embedded software content in chips, the time needed for verification may get worse still.
Moreover, embedded software development mandates the use of software debuggers. Custom logic blocks need accurate RTL simulation with access to waveforms. Peripherals require accurate simulation to verify the interaction between device drivers and peripherals, as well as efficient transfer of data in and out of the chip.
That’s why the demand for new and better verification and validation tools continues to be strong and unabated. And each year, a multitude of verification products and solutions are proposed. Exhaustive functional verification using a software simulator is not a viable solution any longer because of the simulator’s unsatisfactory performance. Simulation farms do not address large designs either since they require long sequences of tests that consume billions of cycles.
Believe it or not, what’s old is considered new again. Emulation solutions –– hardware platforms used to accelerate the chip verification process ––, in particular, have re-emerged as the effective tools for beating these challenges.
Of course, older generations of hardware emulators have been knocked for their prohibitive cost of ownership and limited adoption to a few units at large corporations with generous budgets. These days, an emulation platform, based on new techniques and technology, is much more cost effective and is especially useful when the task calls for executing billions of verification cycles in less than one hour. In fact, many design teams view emulation platforms as a necessary tool for accelerating verification testing.
Emulation offers design teams visibility into the hardware, and helps them to analyze, benchmark and measure SoC performance with realistic scenarios by running at speeds that are close to real-world situations. It is proving to be the tool to accomplish the verification and validation task within a practical time frame. The ability to test a design at very high speeds with visibility into total system behavior prior to silicon has proven to be a boon for the verification and validation flow.
What’s not to like? They accelerate the time required to develop and validate hardware or embedded software design within a constantly shrinking schedule. Emulation allows for more testing to be done earlier in the design cycle to better manage the process and ensure verification and validation goals are met. They improve the product quality by increasing the level of testing of a design to meet the quality standards expected in today’s electronics products. Consisting of a small number of large FPGAs and providing tens of million ASIC-equivalent gate capacity, these emulators are straightforward to set up and easy to learn. And, they are packed into a small footprint.
Physical design will continue to razzle and dazzle the design world, but workhorse verification and validation tools such as emulation will save the day (or silicon)!
Lauro Rizzatti is general manager of EVE USA. He has more than 30 years of experience in the EDA and ATE industries, where he has held positions in product marketing, technical marketing and engineering. Prior to joining EVE, he held various positions in companies such as Get2Chip, Synopsys, Mentor Graphics, Teradyne, Alcatel, and Italtel. Rizzatti has published numerous articles and technical papers and has presented at international technical conferences. He holds a doctorate in Electronic Engineering from the Universita` degli Studi di Trieste in Italy.
San Jose, CA
Reprinted from DACeZine (June 25, 2009 issue) with permission.