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Mentor Graphics Completes Test Chip with IC Implementation Flow for Common Platform 32/28nm Technology

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WILSONVILLE, Ore., January 17, 2010 - Mentor Graphics Corporation today announced it has collaborated with the Common Platform Alliance (CPA) members, IBM, GLOBALFOUNDRIES and Samsung, to design a test chip using its netlist-to-GDSII solution for CPA 32nm and 28nm high-k metal gate (HKMG) IC manufacturing technologies. The Mentor Graphics solution, which includes the Olympus-SoC place and route system and the Calibre physical verification and DFM platform, addresses customers’ requirements for early signoff quality manufacturing (DRC/DFM) closure, multi-mode multi-corner (MCMM) timing/SI closure, low power design and fast time to market.

“The Mentor implementation flow addresses many of the key challenges of IC design at advanced nodes,” said Andy Brotman, vice president of design infrastructure at GLOBALFOUNDRIES, on behalf of the Common Platform Alliance. “By collaborating closely with Mentor, we are able to address many new critical advanced process design constraints, providing fast, reliable design closure even with much larger designs and more complex designs rules. This tight collaboration will help us provide our customers with the fastest time-to-market on advanced technologies.”

The Olympus-SoC physical design system was architected from the ground up to address the key implementation challenges of IC design at advanced nodes. It provides native concurrent multi-corner multi-mode (MCMM) optimization, automation for all low power design methodologies, 100M+ gate capacity, and the industry’s premier parallel timing engine to deliver efficient scaling on multicore, multiprocessor computing platforms.

The Olympus-SoC router provides support for complex 32/28nm DRC/DFM rules and recommended rules for yield improvement at leading foundries. Its “Open Router” architecture enables native invocation of Calibre engines during design. Using this interface, the Calibre InRoute™ manufacturing closure solution provides sign-off quality checking and repair during physical design within the Olympus-SoC cockpit. The Calibre golden signoff platform provides automated antenna fixing, optimized wire spacing, redundant via insertion, smart metal fill, and ERC checking in addition to DRC and LVS.

“Our solutions for the Common Platform design enablement ecosystem are a result of close technical cooperation between the CPA and Mentor,” said Shankar Krishnamoorthy, chief scientist of Mentor’s place and route division. “It all works to provide our mutual customers with leading process technology, multiple manufacturing resources, and better performance and improved time to market for their IC products.”


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