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First Look At NXPís Low Power Solutions for 2011
ARM Techcon Ė November 12, 2010 -- One of ARMís best customers in the semiconductor industry is NXP Semiconductors. I can say that with complete confidence, because 100 percent of NXPís technology forecast is based on ARM processor IP. Everything they ship into the marketplace uses ARM technology.
Next year, NXP will be releasing the LPC 1100, a new family of low power devices.
“We’re very much focused on the lower left corner of the power spectrum,” said Tony Xia, product marketing manager at NXP Semiconductors, at an ARM Techcon seminar. Xia explained that the company’s focus is on delivering optimized solutions for the 8-, 16- and 32-bit microcontroller market.
NXP has had great success in this area with the LPC 1100, which was announced at the end of 2009. Next year, the company plans to follow on this success with the LPC 1200, featuring a highly optimized Cortex M0 processor IP.
“We’re going to be delivering superior code density with 16-bit wide instructions and 64 kb of address space to optimize the efficiency of the M0 instruction set,” said Xie. “Using CoreMarks benchmarks, we’re estimating a 40-to-50 percent smaller code size than some of the typical 8/16-bit cores on the market now.”
Like many other companies in the ARM ecosystem, NXP is tackling the power efficiency challenge from multiple angles.
“When you think of power savings in a microcontroller, you also have to think in terms of time,” said Xie, referring to the time necessary to execute an instruction set. At this level, the longer it takes to complete an instruction, the more power you’re using to get the task done. “We’ve found away to reduce power from 150 mA to 130, which we believe is the industry’s lowest active current. Our goal by the end of the year is to get it down to 100mA.”
In addition, NXP is using other techniques such as sleep mode for non-active blocks, enabling a 3x reduction in power consumption. For instance, he said, the LPC1102 has 11 highly functional GPIOs operating at 130mA. A new version of the device, the LPC1200, adds more peripherals and increases the bus size to 128 bits wide. It also adds key communications IP such as DMA and a 10-bit, 8-channel CRC and contains twice as many comparators as the earlier version. And it still operates at 130mA.
For 2011, Xie said, NXP is focused on three power optimization areas. “First, we’re looking at CPU performance,” said Xie, “We want the microprocessor to operate as fast as possible without increasing the clock cycle. We believe we can achieve a performance increase of up to 30 percent.” Again, the assumption here is that the faster you can execute an instruction, the less power you use to get the job done.
“How will you do that?” asked an audience member. “Unfortunately I can’t tell you that,” said Xie with a smile, “except that it involves intelligent IP within the microcontroller.”
Xie said the second area of power optimization involves drawing the lowest possible current. The plan here is to achieve the lowest possible active power mode while optimizing power down modes to achieve a 30 percent reduction in power.
Finally, Xie said a third option involves optimizing for power efficiency. In this case, the plan is to dynamically balance active mode power for optimal performance.