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Cadence and ARM to Create an ARM-Optimized System Realization Solution

Cadence-ARM

July 21, 2010 Cadence Design Systems, Inc. today announced a broadening of its existing collaboration with ARM to develop an optimized System Realization solution for ARM processors that will enable an end-to-end flow including a full set of interoperable tools, ARM processor and physical IP, services and methodology from embedded Linux to GDSII. To accelerate adoption of this solution, Cadence will provide a full complement of tutorials and education materials including two methodology reference books and extend their ecosystem of service, methodology and training providers.

To deliver this solution, Cadence will take the following actions:

  • support embedded software optimized for ARM processor-based devices in the company’s recently announced IP stacks
  • enhance the interoperability of ARM tools and IP including ARM DS-5 and RealView Development Suite, Fast Models, and VSTREAM transactor with Cadence Virtualization technologies
  • expand its existing collaboration on AMBA IP-VIP pairs and interconnect fabric, and reference methodologies for design, verification, and implementation

Ran Avinun, Group Director, System Design and Verification Product Management at Cadence, explained to Low-Power Design that Cadence has long been working with ARM to provide comprehensive AMBA Verification IP with a Compliance Management System (CMS) tied directly to the ARM spec.  Now ARM assertions and coverage points will be included in CMS making it even more straightforward for end users to quantifiably measure coverage relative to the ARM spec. This collaboration is being extended to support UVM (Universal Verification Methodology), AMBA 4, and performance estimation for the ARM fabric.

Beyond its work with ARM, Cadence is extending the System Realization ecosystem through new collaborations with service, methodology and training providers that will help accelerate customers’ deployments of system-level solutions. The new companies include Australian Semiconductor Technology Company (ASTC), Chubu Toshiba Engineering Corp, CircuitSutra, CM Engineering Co. Ltd., HDLAB Inc., Nippon Systemware Co. Ltd., and Toshiba Information Systems (Japan).

To further help customers achieve efficient, cost-effective adoption of System Realization aspects, Cadence has developed the industry’s first transaction-level modeling (TLM) design and verification methodology, available to the industry in its newly published book titled, “TLM-driven Design and Verification Methodology.” To accelerate SoC integration and verification based on the recently standardized Universal Verification Methodology (UVM), Cadence also has released another new book titled, “A Practical Guide to Adopting the Universal Verification Methodology (UVM).” Together, they provide a pragmatic set of best practices to help accelerate solution deployments.

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