Pravin Madhani, GM Place & Route Division, Mentor Graphics
Video interview with Pravin Madhani, GM of Mentor Graphics Place and Route Division, by John Donovan, Editor/Publisher of Low-Power Design. Conducted at the EDA Tech Forum in Santa Clara, CA, September 9, 2009. In particular we wanted to know:
Just how do your place and route tools interact with the other design tools in the tool chain? Do they rely on a common database, or do they accept constraints from the tools above them in the tool chain or design rules from the foundry?
At 32 nm and below a few atoms difference in doping can cause a gate to fail. How can you do reliable physical verification considering the wide variations that can be expected during manufacturing?
How exactly does multi-corner, multi-mode optimization work? How might it help—and to what extent can it be effective—in increasing the energy efficiency of an SoC design?
Finally, what are the major hurdles that physical design and layout software have yet to surmount, and what sort of progress can we hope for in the next few years?