FPGAs to the Rescue
Every system designer today worries about three things: size, power and cost; for a designer of a portable device these are can be nightmares. We as consumers want every feature we can get in our MP3 players, GPS units and smart phones. Of course, we want to pay nothing for these devices, we want them to be small enough to blend in with the surroundings, and we don’t want to ever recharge their batteries in our lifetime! But, to the system designer’s dismay, each added feature increases size, cost, and power. Fortunately, a new class of, small, low-power, inexpensive Field Programmable Gate Arrays (FPGAs) is rescuing portable system designers.
Historically, the high power consumption of traditional FPGAs has kept them out of the portable devices market. Instead, small Complex Programmable Logic Devices (CPLD – a less expensive, less sophisticated, skinnier cousin of FPGA) were used in portable devices to provide some basic programmability and to do some rudimentary operations such as voltage level shifting and port enhancement. However, the recent emergence of ultra-low-power FPGAs with high logic capacity, such as the iCE65 FPGAs from SiliconBlue Technologies, has opened new possibilities for portable systems designers. As a result, FPGA applications, which historically could only be used in bigger power-hungry systems with elaborate cooling mechanisms, can now nicely fit in a handheld device (without burning our hands).
One such application is to utilize the FPGA as a “coprocessor” – a secondary processor that can offload applications otherwise performed by the main application processor. In traditional embedded system designs, the idea of an FPGA coprocessor is to achieve some form of code acceleration by identifying and converting computationally intensive algorithms into FPGA hardware. But in low-power, consumer product applications, the primary goal of an FPGA coprocessor is to save power by offloading tasks from the application processor. One such task is simply blinking the Bluetooth LED every half second. Obviously the system’s ARM processor is more than able to handle this. However it’s a bit like using an eighteen wheeler to take a letter to the post office. Better to keep the system processor in deep sleep mode, and offload LED blinking to a small, low power FPGA.
A more complex example is MP3. Often the application processor is used to decode the MP3 and send the audio data to a DAC or Bluetooth module. This means the power hungry applications processor is running for the entire time that the MP3 is playing. A better option would be for the applications processor to place the MP3 file in a buffer, let the FPGA decode the MP3 and stream it out to the DAC, while the applications processor stays powered down.
But using an FPGA to implement a power saving MP3 coprocessor is only one of many such applications. Today’s portable world is dominated by convergence – our cell phone is no longer just a phone; now it is also an audio/video player, a camera and a GPS. These new multi-function devices are posing a new power consumption challenges for designers: a device may have long battery life when used solely as a phone, but it may drain the battery much quicker when it plays video.
As with the MP3 example, an applications processor running at full speed, communicating with the video CODEC and media FIFO does not achieve optimum power consumption. Here is another place where an FPGA coprocessor can come in handy. It can be configured to perform the CODEC and FIFO functions at much lower power than the applications processor, thus increasing battery life. Smart phones have an LCD timing controller that connects the CPU to the display. This is another function that an FPGA coprocessor can offload. Each time a low-power FPGA coprocessor offloads an applications processor task, the net result is power savings.
So why not just use an ASIC? One immense benefit of using an FPGA coprocessor over an ASIC or ASSP SOC is its re-programmability. Say, an engineer needs to upgrade the video functionality in an existing applications processor to MPEG4, in order to enable some new video features in a smart phone design. Using an ASIC or ASSP, could easily require several months, and would incur fabrication costs. In contrast, an FPGA implementation could be done in as little as a week, and has no fabrication cost.
With the availability of new, small, ultra-low-power FPGAs, the FPGA cost, flexibility and time to market benefits enjoyed by wall-plugged devices can now be applied to power and space constrained handheld devices. The smart use of an FPGA can significantly enhance the battery life and the new marketing claims, such as, "10 hours of MP3 play time," "6 hours of GPS," etc., are not as far-fetched as they may have once seemed.
SiliconBlue Technologies Corporation
This article first appeared in the January, 2009 issue of Portable Design. Reprinted with permission.