The Design and Verification Challenge for the Next Decade
Interfacing digital circuits with the analog world has always been challenging. At smaller geometries it gets a lot harder.
“The real world is analog and computers are digital.” These nine words set the stage for the great circuit design challenges of the next decade. To quote G. Dan Hutchenson, president of VLSI Research, “virtual reality is possible only with mixed-signal chips,” and of course, every designer on the planet, from the creators of advanced weaponry to smart phones and cars that nearly drive themselves, is hot on the trail of virtual reality.
Most current EDA methods and the tools that support them are inadequate to the task of designing for the “real world” for to do so they must account for an enormous number of design considerations. The list is long and daunting for every application and includes process, voltage and temperature (PVT) variation, power consumption, process constraints and yield requirements.
Big, Complex and Getting Worse
It was the invention of the transistor that made it possible for engineers to outsmart the physical laws governing electrical circuit behavior and represent much of it instead in binary logic. In an electronic version of “the more things change, the more they stay the same,” digital is now becoming analog, as submicron processes require engineers to deal with the parasitic effects that result from the analog behavior of all electrical circuits.
Analog signals are a natural part of all continuous applications, including audio, images and sound. Analog circuits provide the interface to these real-world sensory applications and to the digital world of processors and memory. The most common analog applications performed in silicon include amplifiers for power and signal amplification, clock systems, frequency control systems implemented with phase-locked loops (PPLs) designs, filters, synthesizers and transceiver circuits for wireless access.
All of the major electronic market areas including consumer electronics, automotive and telecommunications – three of the fastest growing markets over the last 10 years and predicted to remain so over the next 10 - require some type of analog interface to the digital portion of the device, and more and more this is being accomplished by putting both analog and digital on a single chip. Analog/mixed-signal design and verification has become the chip design and verification challenge for the next decade.
Although the precise number of mixed-signal design starts is difficult to estimate, a number of major EDA (electronic design automation) tool providers indicate that the majority of their customers are increasingly moving to mixed-signal designs. One major EDA company notes that more then 20% of its customers are working on chip designs to be used in wireless end applications alone. Industry analysts have estimated that 80% of all IC designs today are mixed signal.
Analog design remains devilishly difficult when compared to digital due to the extreme variability of the individual devices, up to ±20%. In addition, the device properties often vary between each processed semiconductor wafer (Figure 1). Slight changes to the amount of diffusion time, uneven doping levels, etc. can have large effects on device properties. Analog components also become more complicated as available bandwidth and frequencies increase. And then there is the fact that nothing stays the same. Mixed-signal chip design must constantly adapt as wireless protocols and technology change.
Figure 1: Site-to-site process variation on a wafer and wafer-to-wafer process variation across wafers
Mixed Signal is a Marriage with Relationship Issues
In the ancient days of the 1970’s and 1980’s, analog and digital functions were handled by separate chips. As computers continued to shrink and morph into battery powered mobile devices like phones, iPods and games and provide the brains for safety critical “by wire” applications that have to “think” like computers but also interact real-time with the real world - the mixed-signal chip age was upon us. It came complete with a stunning promise to support size, low power, reduced cost, and on the dark side, the design and verification challenges we are still struggling with. To a large degree although the chip may have integrated analog and digital functions the design processes remain separate - and there in lies both the problem and the opportunity.
From its lowly origins in simple devices such as sensors and automotive controls to today’s smart mobile devices, the importance of mixed-signal design and verification has increased 10 fold in the last 10 years. The continued meteoric rise of the wireless market will drive mixed-signal design and verification to new levels of complexity as their digital capabilities leverage analog functionality. Even in the soft economy of 2008-2009 leading analysts at Gartner report key segments of the market, such as Smart Phones, grew nearly 14% worldwide. Global sales of smart phones for the year 2008 reached 139.3 million devices, up 13.9 per cent compared with 2007.
Designing a chip that processes analog and digital signals, as well as the radio-frequency (RF) signals needed by handheld devices, is difficult because the signal domains have significant technical differences. Typical analog components include digital-to analog signal converters, resistor functions, battery and power-supply control functions, signal amplifiers, and application- specific components, such as temperature or motion interfaces in sensor devices. Digital components include a microcontroller or microprocessor, memory, ADC (analog-to-digital converter), and an interface bus. New approaches to design, such as digital signal processers, had to be created to bridge the high-frequency analog or RF wireless signals in GHz range to the lower frequencies used in digital signal processing in kHz range. But robust design and verification tools to automate mixed-signal design have languished.
For example, Monte Carlo Analysis is integral to the most common simulation techniques used to verify analog designs in nanometer process technology. This method predicts how well a transistor-level design will meet specifications and yield once manufactured. The problem with overreliance on this technique is that Monte Carlo analysis by itself provides no granularity to the designer beyond how well the circuit may yield. There is no information as to why the circuit is failing or what the yield-limiting issues are or how to optimize the tradeoffs between circuit yield and performance.
For the design of the analog portion of the chip there is no equivalent to digital synthesis let alone newer techniques like formal verification. Probably the most common technique designers use to make up for the last of robust analog and mixed-signal design and verification automation is to over-design their circuits, guard-banding designs by including excessive safety margins. Such over-designing leads to ICs that are more conservative than necessary in power, area and performance specifications. The never ending march toward smaller geometries is increasingly less forgiving of over-design. New methods and tools are critical to analog mixed-signals design and verification efficiency, especially below 65 nanometers.
Creating a Modern Transistor-Level Design and Verification Framework
Designers desperately need a comprehensive transistor-level design and verification framework comprised of methods, tools and underlying algorithms up to the task of analyzing, optimizing and verifying mixed-signal circuits within the given statistical manufacturing variations - and well before tape-out. This is no small task. Today’s nanometer designs consist of literally thousands of variables that do not lend themselves well to simplifying assumptions.
Currently, digital circuit designers have a rich portfolio of computer-aided design tools. Analog designers have relatively few but progress is being made. It has been nearly a decade since the IEEE and Open Verilog International adopted hardware description language standards for analog and mixed-signal design tools. For example, analog extensions have been added to Verilog and VHDL, Verilog AMS and VHDL-AMS. Still analog does not have a robust synthesis capability like Synopsys Design Compiler which in the digital world can go directly from RTL to gates.
Most leading companies have turned to a top down flow and methodology to divide and conquer the problem. One common practice is to verify the digital design portion represented in Verilog or VHDL and use digital pseudo models for the analog blocks. The downside of this flow is that there is a specific step required to create the digital pseudo models.
SPICE simulators remain a critical part of analog mixed/signal verification. SPICE programs perform mathematical simulation of a circuit’s behavior based on the circuit net list description of the components in a circuit and how they are connected. SPICE simulations are notoriously slow for complex circuits that typically must be analyzed for a number of factors including noise, jitter, reflection, and crosstalk. The slowness of traditional Spice has led to the development of Fast Spice where substantially greater performance can be achieved but at the expense of accuracy. Some of the more popular commercial versions of fast SPICE include Adit, Ultrasim, NanoSim, and HSIM.
The most sophisticated mixed-signal tools such as those from Cadence Design Systems and Mentor Graphics (Figure 2) combine technology that is capable of simulating transistors and both the standard analog mixed-signal and digital languages. This enables multi-level verification where the critical path of functionality is represented at the transistor-level and other blocks of the design are represented as high-level behavioral models. Also with this approach, the behavioral models written during the top-down design phase are potentially reusable for the bottom-up verification step.
Figure 2: Mixed-signal simulation flow using VHDL-AMS behavioral modeling of the analog blocks and Mentor Graphics Questa ADMS – this approach took the simulation time of a mixed-signal design down from over 16 hours to 3.7 seconds.
Arming Digital Designers to Deal With Increasing Amounts of Analog
Transistor-level design is complex. Whether it is analog/mixed-signal, custom digital, or memory integrated circuit design, an enormous number of design considerations must be accounted for simultaneously. Dozens of specifications, environmental conditions, process corners and global and local statistical variations must be considered. Do the blocks fit together at the top level? Are they functionally accurate? How do you verify the entire design? What tools or methods can yield complete full-chip parasitic netlists? And if you could create it what tool could simulate it?
There is no doubt that digital designers, to whom most often the full chip verification falls, do need 100% automation in analog/mixed-signal….unfortunately 100% is not possible today, and probably never will be. Digital designers, and their analog brothers, have been misled. A false analogy has been promoted by industry pudants and some in the EDA industry between analog and digital design. The idea was that just as in digital, you would be able to specify your analog mixed-signal design at a very high-level and then the transistors would be automatically implemented. This has proven to be absolutely impossible for complex designs. Full analog synthesis of complex circuits is a lovely dream but not practically possible with today’s technology. Analog design is more like system design, an extremely creative process and many believe that it will never become a direct mapping of equations into gates.
The original concept of “analog synthesis” was such an overblown idea that it produced a number of EDA startups with smart people and good intents. Unfortunately, it was impossible to convert the concept into anything real. It is time to redefine “analog synthesis” in more modest terms. The place to start is with layout automation, tools that “assist” the engineer to place, size, perform corner analysis and extract information.
Sanity comes from accepting the fact that analog mixed-signal design and verification effectiveness comes more from the ability of the design organization to develop and implement a “systematic design methodology” than from end to end automation. Better automation for analog layout is a good place to start. Today there are tools from Mentor Graphics and Cadence Design Systems (as well as a number of start ups) that provide automatic analog layout capability to assist with new design creation and also help generate a new layout incorporating the target technology process and the target transistor sizes. This is “analog synthesis” in the small but one that promises big gains.
Parallelizing Analog and Digital Design
Even though they occupy a small portion of the total chip space, analog and mixed-signal design issues will continue to consume disproportionate chip-design resources. As more and more systems-on-a-chip include analog and mixed-signal components, digital designs will deal with increasing analog I/Os and intellectual property (IP) cores and libraries. This increased level of integration puts tremendous pressure on designers. Traditional design tool flows force designers to develop analog and digital subsystems in isolation, delaying the integration of these components until IC layout and the testing until after fabrication.
Simple chips with unidirectional analog/digital interaction can probably be verified effectively with separate analog and digital simulation flows. For more complex chips detecting design flaws prior to tape-out requires the most advance mixed-signal simulation tools. What is required is a true mixed-signal verification platform that uses mixed-signal standard languages while maintaining a unified simulation environment. Designers need to be able to combine VHDL-AMS, Verilog-AMS, VHDL, Verilog, SystemVerilog, SPICE and SystemC anywhere, and at any level, in the design. This enables concurrent simulation of analog blocks described in transistor-level as well as Verilog-AMS and VHDL-AMS models, the same analog behavioral languages that are used during the top-down design phase (Figure 3).
Figure 3: Mixed-signal design flow
One such tool set is Questa ADMS from Mentor; Questa ADMS gives designers a comprehensive environment for verifying complex analog/mixed-signal System-on-Chip designs. Questa ADMS combines four high performance simulation engines in one efficient tool: Eldo for general purpose analog simulations, Questa for digital simulations, ADiT for fast transistor-level simulations and Eldo-RF for modulated steady-state simulation.
Analog and mixed-signal SoC designs combine analog and digital content more tightly than ever before. They increasingly depend on integrated analog blocks such as A to D and D to A converters, phase-locked loops, and adaptive filters. This increased level of integration puts tremendous pressure on designers. Traditional tool flows force designers to develop analog and digital subsystems in isolation, delaying the integration of these components until IC layout and the testing until after fabrication.
Improving analog mixed-signal design and verification requires moving to a mixed-signal design methodology and implementing true mixed-signal simulation that supports VHDL-AMS, Verilog-AMS, VHDL, Verilog, SystemVerilog, SPICE and SystemC anywhere, and at any level, in the design—in a unified simulation environment.
Mentor Graphics Corporation