Tag Archives: Energy Efficiency

Where is the next factor of 10 in energy reduction coming from?

Over the last decade chip engineers have come up with a large number of techniques to reduce power consumption: clock gating; power gating; multi-VDD; dynamic, even adaptive voltage and frequency scaling; multiple power-down modes; and of course scaling to ever … Continue reading

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How Green Is Your MCU?

With energy efficient, ‘green’ designs devices being all the rage, embedded developers need to be asking semiconductor vendors, “How green is your MCU?” (OK, so it’s black. Work with me here.) Ever since Intel hit the Power Wall in 2004—when … Continue reading

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Ultra Low Power Electronics in the Next Decade

As a TI Fellow and director of TI’s Kilby Research Labs, Ajith Amerasekera’s job is to predict the future and plot a roadmap to it. His keynote at day two of the low-power electronics show (ISLPED) in Austin—“Ultra Low Power … Continue reading

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For Energy Efficiency, Forget Accuracy

U.C. Berkeley professor Jan Rabaey kicked off the 2010 International Symposium on Low-Power Electronics and Design (ISLPED) today in Austin with a challenge to programmers, hardware designers and their EDA tool providers: The deterministic Turing model has hit the power … Continue reading

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Low-Power Design Has a High-Power Payoff

The New York Times ran a story this morning that speaks directly to engineers involved in low-power design: Plugged-In Age Feeds a Hunger for Electricity. The message and the challenge are clear: “Electricity use from power-hungry gadgets is rising fast … Continue reading

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