“Oh, East is East and West is West, and never the twain shall meet.”—Rudyard Kipling
Kipling’s line goes back over 100 years but today it could just as well apply to digital and analog engineers. Engineering graduates for at least the last 40 years have been highly skilled in the latest digital design techniques but only passably literate in analog design, a black art practiced by unkempt, bearded über-bright guys like Bob Pease. System architects would partition designs into their digital and analog components and toss each over the wall to their respective design teams, who would meet again at the RTL stage only to discover that their work products didn’t mesh.
With most designs today involving mixed-signal design, those days are over. However converging the tools, techniques, and mindsets of digital and analog designers is still a work in progress. On September 20th Cadence put on a one-day Mixed-Signal Technology Summit to address those issues. Not coincidentally the Summit coincided with the publication of their Mixed Signal Methodology Guide.
Chi-Ping Hsu, Cadence’s senior VP of R&D for Silicon Realization, kicked off the day pointing out the importance as well as the challenges of mixed-signal design. Over the last four years Cadence has spent over $50 million designing mixed-signal design tools, and it currently employs over 2,000 R&D engineers trying to stay ahead of the curve. Chi-Ping explained that Cadence had started working on low power in 2006 and has built its design flow around a matrix-driven verification methodology.
Professor Ali Niknejad of UC Berkeley’s wireless lab gave the Academic Keynote. Prof. Niknejad focused on designing 60 MHz chips. His lab has produced a 60-GHz transceiver that can transmit at 40 dBm ERP at a shorter range but far higher data rate than Wi-Fi. CMOS devices operating at up to 300 GHz FT are available; interconnects and passives are now the main constraints. PAs at these frequencies usually run Class D modulation, displaying up to 77% efficiency. PAs are acting as DACs at RF frequencies, oversampling and then filtering to remove spectral lines. According to Prof. Niknejad the main EDA challenge at these frequencies is simulating the designs. In addition, “We need better AMS tools and designer training.” In summary: “If you want to innovate with deep CMOS technologies you have to be a mixed-signal designer.”
Chris Collins, the director of TI’s analog division, gave the Industry Keynote. Collins couldn’t resist urging Ch-Ping to spend more on mixed-signal design tools, since TI has spent over $9 billion on analog and RF designs, a lot of that having been spent trying to get their analog tools to play nicely with their digital and RF counterparts. Collins’ talk Mixed-Signals: Tribulations of Combining Analog and Digital Design drew on TI’s long history of wrestling with the problem. His key points are worth noting:
- Pure analog designers need to stop doing digital
- Mixing of signals between digital and analog partitions of designs is tightly coupled more than ever
- Languages and data type connection challenges are increasing, giving simulation performance improvements an uphill task
- Setup and debug time are becoming critical measures in meeting verification deadlines
- Having a plan configuration management and discipline is key, if you don’t think it is you need to wake up
Long story short: Collins suggested adding digital engineers to analog design teams and analog engineers to digital teams. If you have one combined team and the top layer of the SoC being designed is digital, put a digital engineer in charge; if it’s analog, put an analog engineer in charge.
Next up was Mladen Nizic, engineering director of Cadence’s Mixed Signal Solution division, who reassured the audience that Cadence was on the case. In particular he focused on the low-power challenge in mixed signal design resulting from increasing digital content, increasingly complex LP techniques deployed in IP, and the burgeoning AMS verification issues that result. Cadence Virtuoso AMS Simulation pays special attention to connecting modules in analog-digital co-simulation, converting corrupted digital values into analog values. Virtuoso Power Intent Export Architect generates CPF macro models from schematics and inherited connections; it then generates a structural netlist for use by Encounter Conformal Low Power (CLP). CLP performs structural and functional static checks; it is test bench independent while being fast and comprehensive.
Panel: “Are We Closing the Gap in Mixed-Signal Design?”
After numerous other speakers attempted to demystify mixed-signal design, the afternoon wrap-up panel “Are We Closing the Gap in Mixed-Signal Design?” brought both optimism and skepticism to bear. Experts from Maxim (Neyaz Khan), Broadcom (Nishant Shah), IC Manage (Shiv Sikand), TI (Bill Meier), and Cadence (Bob Chizmadia) all agreed that mixed-signal design tools have come a long way, especially since what TI’s Chris Collins said earlier referred to as “the dark ages of mixed-signal design” from 1995 to 2005. However they also agreed that with the explosion of chip complexity at smaller geometries – to which digital can scale much better than analog – the EDA tool makers are going to have to keep innovating quickly to stay ahead of the curve.
IC Manage’s Sikand listed the main challenges for mixed-signal design as internal IP reuse; SoC assembly; network storage bottlenecks; and bug management. All the panelists agreed with him that “getting knowledge across the design team is very important.”
The interface between digital and analog is where the rubber meets the road; converting 1’s and 0’s into a continuously variable range of voltages isn’t an easy task. Cadence’s Nizic had explained earlier that Virtuoso creates connectors that link analog blocks into an otherwise digital design. Broadcom’s Shah suggested that “AMS connect modules need more enhancements,” including support for multi-power domains in particular. Maxim’s Khan was more direct: “Somebody throws in a level shifter and all hell breaks loose.” You could wind up with back to back level shifters surrounding each analog block—not a pretty picture.
While TI’s Meier lamented the fact that “connect modules don’t have the ability to track analog voltages”—and therefore CPF has no way to do so—he did offer that “CPF is the way to go for connect modules.” The problem right now is, How do you verify that you’re not in a power down condition? You can do static checks but nothing for dynamic verification. Meier would like to see SystemVerilog connect module assertions, which would address the problem that currently there isn’t an assertion that works throughout the entire simulation flow.
Someone from Cadence R&D assured the panelists that Cadence has made a lot of progress on the connect module problem and is addressing the other pain points they’d listed.
It fell to Cadence’s Bob Chizmadia to wrap it up. He pointed out that Real Number Modeling (RNM) has gone a long way toward addressing the analog-digital conversion problem, which he feels is well within reach at larger geometries. However, “We’re not there yet at advanced nodes—20 nm on down” where “the system implementation is daunting.” Variability at those line widths greatly restricts how you design, and parasitics have exploded. Bottom line: “We’re still trying to figure out how to do it.”
All told the conference was very data intensive, and judging by the large number of questions very useful for AMS designers. Design complexity may be exploding, but if anyone at the conference felt daunted it wasn’t apparent. After all, engineers enjoy challenges and AMS design offers plenty of those.