Category Archives: Low-power design

When Low-Power Design Gets Personal

I lost my hearing in Hong Kong in 1996. Well, everything much over 1 kHz, that is. By all rights I should have lost it during rock concerts back in the ‘60s, but I guess the crowds made it hard … Continue reading

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Powering Down

Ever since Intel hit the Power Wall in 2004—when the Pentium 4 drew 150W and approached 1000 pins—low-power design has come into its own. Over the past decade smart engineers have come up with a seemingly endless number of innovative … Continue reading

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The Power Wall: Are we scaling it or is it just getting higher?

Cadence hosted a Low-Power Summit this month at which Jan Rabaey was the keynote speaker. Jan is the Donald O. Pederson  Distinguished Professor in the EECS department at U.C. Berkeley; Scientific Co-Director of the Berkeley Wireless Research Center (BWRC); and … Continue reading

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