So called “cloud computing” is the presumptive wave of the future, and not just to deliver software-as-a-service (SAAS), which will certainly challenge Microsoft’s business model. The ‘cloud’ is of course all those mainframes that Amazon, Google, Rackspace and others use to deliver services over the Internet, not to mention to your iPhone and iPad. Susan Peterson, Cadence’s Group Director of VIP Product Marketing, got my attention this week when she remarked off-handedly, “For every 600 iPads a server is born.”
Low-Power Design hasn’t been paying much attention to servers, but we should. It takes a lot of energy to move data around. Two data points: (1) server farms account for over 3% of the total energy consumption in Europe; (2) using figures from Dataquest I calculate that just moving the cellular traffic in the U.S. and Europe in 2015 will require the equivalent of six new 100 kW power plants. The cloud is very energy intensive to the point where you have to wonder whether the current course is sustainable—or at least at what price.
One way to save energy, of course, is to move data more rapidly—bursting it across the dataplane (whether wired or wireless) as quickly as possible—which with extremely data intensive devices like the iPhone and iPad is a necessity. One group working hard on that issue is the PCI-SIG, who recently announced that PCI Express (PCIe) 4.0 will be able to be able to handle 16 gigatransfers per second (GT/s), double the bandwidth over the PCIe 3.0 specification at approximately the same power levels. Another way to look at is servers will be able to handle twice the data at the same power level. That’s only part of the solution, but it’s real progress.
Go with the Flow
But as Peterson pointed out, even with a well defined specification integrating PCIe IP into a complex SoC—not to mention a complex design flow—is a non-trivial task; then comes the far more tedious task of verifying that all the various pieces of IP play well together. That was the point of Cadence’s announcement at this week’s PCI-SIG Developer’s Conference of support for the pending PCIe PIPE4 (PHY Interface for PCI Express) specification; Accelerated PCIe VIP (AVIP); and its TripleCheck test suite for testing full PCIe compliance throughout the design process.
How do you take the PCIe specification smoothly through simulation, acceleration, and emulation, verifying each step of the way that all your IP is working smoothly together? Peterson walked us through how Cadence approaches the problem:
Each design team’s development cycle varies but they generally start from architectural exploration and conclude with a working prototype.
Software simulation is used predominately in the earlier phases during late architecture exploration, to algorithmic verification through block or IP design and verification. As users move to chip/system level validation (often including software) they often need more performance than simulation can provide.
Using Cadence’s Palladium Verification Computing Platform (VCP) users can use one single compute resource to span all the way from signal-based acceleration to In-Circuit Emulation. Each use mode is now described along with the Accelerated VIP (AVIP) use mode to support it.
1. Signal-based acceleration increases speed over simulation while retaining the same UVM testbench. Only the DUT is accelerated; the interaction between software and hardware remains at the signal-level. Cadence AVIP’s UVM use model supports signal based acceleration.
2. Transaction-based acceleration (TBA) provides additional performance, in some cases, even up to MHz speeds but more likely hundreds of KHz. The design and portions of the testbench are accelerated with the interaction between software and hardware raised a level of abstraction to the transaction level. TBA offers the unique benefits of maintaining interactive debugging capabilities and the look and feel of a simulator. This makes it easier for design and verification engineers to adopt transaction based acceleration. The hardware can be viewed simply as an added, higher speed compute resource. Cadence AVIP’s UVM and C interfaces support this Palladium use mode.
3. In synthesizable-testbench mode (STB) both the DUT and the testbench are accelerated. This, of course, requires that the testbench be compiled in the emulator. Cadence AVIP’s embedded use mode supports this Palladium mode.
4. In-circuit emulation offers the additional benefit of live stimuli and responses, increasing the verification accuracy. Cadence SpeedBridge rate adapters support this use mode.
While Cadence is focusing on PCIe at this week’s show, its Cloud Infrastructure VIP Suite supports not just PCIe but just about every other data transfer protocol you’re likely to find in the cloud food chain.
With not just more data but more processing moving to the cloud, verifying that complex, cloud-based servers work both correctly and efficiently is both increasingly challenging and increasingly critical. The EDA community is tackling the part of the problem it can address, which is a lot of it. With a little luck and a lot of ingenuity we’ll see more and more iPhones and iPads coming online without having to break ground on a batch of new power plants.
