While system-level design has been proceeding apace for many years—approaching the goal haltingly and asymptotically—system-level verification remains the Achilles heel of that enterprise. SoC design in particular increasingly consists of assembling IP from a variety of vendors, reusing some of your own IP, writing new code, and then praying that all these elements work together smoothly—which they almost certainly won’t. You can trust the IP you licensed to work as advertized, but verifying that it works properly in your design has always been a time sink at best. Many, if not most EDA companies have point tools for verification, but to date it hasn’t been possible to even get the tools from any one vendor to work together smoothly across the entire design flow.
Last May Cadence took aim at the problem by announcing its System Development Suite, which introduced its Rapid Prototyping Platform and Virtual System Platform, integrating them with their Palladium XP Verification Computing Platform and Incisive Verification Platform. The goal was a unified system for top-down hardware/software co-design. While still not the Holy Grail of a seamless “algorithm to GDSII” design flow, the combination of four connected platforms did move the ball a lot closer to the goal, creating an integrated simulation-acceleration and emulation environment. Cadence claimed at the time that their approach reduced system integration time by 50%, based in large part no doubt by Palladium’s hardware-assisted emulations. But there was still work to be done.
Today Cadence announced new in-circuit emulation capabilities for its Incisive and Palladium XP platforms as part of its System Development Suite (SDS) as well as acceleration and emulations extensions to its Verification IP Catalog. The result is what Cadence calls “a single heterogeneous environment for system-level verification,” combining the speed of in-circuit emulation with the analysis that’s possible with RTL simulation. Design teams now will have a common, unified verification environment, which Cadence claims can result in “up-to-10x increased efficiency during system-level validation and root cause analysis.”
The addition of Universal Verification Model (UVM)-compatible accelerated verification IP (VIP) further smoothes the transition from simulation to acceleration, in-circuit acceleration, and in-circuit emulation, enabling designers to verify systems that are too large to effectively verify using RTL simulation.
According to Gary Smith, principal analyst at Gary Smith EDA, “The overall plan looks great—they really have done a good job. They’ve got probably a third of it done with this announcement.” What’s the third they’ve accomplished? “Well, they’ve tied the rapid prototype together with the emulator and the simulator. That’s a big breakthrough.” And the remaining two thirds? “Connecting the remaining boxes.” How long with that take? “It’ll take them a couple of years to put it together. It’s a big job…but they really have this whole ESL thing figured out pretty well now. Expect some further announcements later this year.” Stay tuned.