To date winning a cell phone socket has been a bridge too far for FPGA vendors. Xilinx’s CoolRunner CPLDs have been successful there by adding glue logic, but FPGAs have long been too bulky, expensive, and power hungry to get into anything smaller than a military manpack. Startup SiliconBlue intends to change that.
SiliconBlue Technologies has announced that it is sampling its Los Angeles family of low-power FPGAs – the LP series for smart phones and the HX series for tablets. The FPGA fabric routing in the LP series is optimized for low power and in the HX series for speed. Both product lines are based on TSMC’s 40-nm LP CMOS process and achieve, according to SiliconBlue CEO Kapil Shankar, static power of “tens of microwatts for LP and hundreds of microwatts for HX.”
SiliconBlue’s unique contribution is an SRAM-based FPGA fabric that, according to Shankar, “can operate from a 1.0V core and consume 50% less static power and over 50% less dynamic power than 1.8V ‘low-power’ PLD alternatives.” The Los Angeles family tops out at 16,192 logic cells (800K system gates), a good order of magnitude higher than CPLDs, opening up a far wider range of possible applications.
How Did They Do That?
Going to 40 nm certainly helps to reduce dynamic power, since you can drop the core voltage to 1.0V. On the other hand quantum tunneling through very thin gate dielectrics increases leakage current and drains off the charge from SRAM capacitors. SiliconBlue has introduced some ‘secret sauce’ CMOS process improvements and altered the gate geometries to minimize off-state leakage. Their iCE65L04 chip—with 3,520 logic cells or 2,700 equivalent macrocells—draws 26 µA in standby mode.
There are some other interesting tweaks to the usual SRAM FPGA fabric. Instead of constructing LUTs from N-channel transistors, SiliconBlue uses matching N- and P-channel transistors, effectively limiting leakage. The chips use a buffer-free interconnect, dispensing with the usual 4-6 buffers per interconnect. Finally, the routing fabric is designed for minimum leakage, not maximum speed.
Shankar told Low-Power Design that the chips have no static or full shutdown mode, though only the portions of the chip that are actually used are powered up, the rest are shut down; static power is measured at 0 Hz, namely with the clock shut down.
SiliconBlue uses a 2T non-volatile SRAM memory—based on Kilopass’ XPM CMOS NVM process—that avoids the expense of embedded Flash or EEPROM. Traditional floating-gate memories such as EPROM, EEPROM, NOR and NAND Flash as well as SONOS store electrical charges near a transistor gate; at smaller geometries—helped by mobile ion contaminants—those charges can bleed off quickly. SiliconBlue’s Non-Volatile Configuration Memory (NVCM) “uses the controlled electrical change of transistor gate dielectric from insulator to conductor as the basis of the memory.” NVCM blocks are built on the same bulk CMOS die as the programmable fabric, reducing processing costs and die size while adding an ‘instant on’ capability to the chips. The company claims the NVCM blocks take up only 2-5% of the die area and draw 8 µA operating current.
Packaging also targets high-density PCBs. The smallest parts come in a 2.5 x 2.5 mm (0.4 mm pitch) micro plastic BGA package, made possible by using wafer-level chip-scale technology.
What’s a CMD?
You don’t grab handset sockets selling FPGAs. QuickLogic, for example, doesn’t make (OTP) FPGAs, they make Customer Specific Standard Products (CSSPs), a sort of customizable ASSP. SiliconBlue, for its part, makes Custom Mobile Devices (CMDs). Its mobileFPGA chips are “ready-to-use devices that incorporate custom functionality as well as standard building blocks that are standard to handset applications.” The entire chip is programmable, with Silicon Blue offering 50+ “mobileWARE customizable function blocks” to assist in custom designs. Basically there’s nothing custom about Custom Mobile Devices until you customize them yourself or have SiliconBlue do it for you.
If all of this sounds like a marketing pitch, frankly it is. But with impressive power and density figures, coupled with a lot of cell-phone oriented IP, the company is trying to take their chips where no FPGA has gone before. They push the flexibility, time-to-market, and BOM cost reduction arguments, which are all legitimate; the FPGA camp has been making them since Day One, but they’ve only gained traction as power consumption declined and custom ASICs became a game only the big dogs could play.
Still, LA family devices have some clearly targeted uses. SiliconBlue wants its CMDs to be companion chips to existing mobile chipsets, targeting video and imaging, sensor management, memory management, and port expansion. MobileWARE IP blocks support a wide range of protocols useful on handsets, including SLIMbus, DBI, ECI, MIPI-DBI/DPI, WUXGA, DDR 133, SDIO 3.0, and USB 2.0. Considering the increasingly wide range of sensors found in cell phones, CMDs could find full employment interfacing them with the applications processor.
High-speed, high-definition video is another promising area for low-power FPGAs, whose massively parallel structure makes them a natural for an application where DSPs are starting to run out of steam. For imaging the iCE40 features flexible, cascaded BRAM and extra PLLs to support high-speed LVDS signaling. iCE40 CMDs can stream video at 525 Mbps, enabling HD720p (1280 x 720) at 60 Hz and HD1080p (1920 x 1080) at 30 Hz.
Despite having a low profile in the U.S., SiliconBlue has some major design wins in Asia. Shankar claims the company has shipped 7 million of their 65-nm devices to over 250 customers, including tier one customers like Samsung and Huawei. Their chips are found in 30-40 products to date, including smartphones, cameras, personal media devices, and e-books.
The iCE40LP8K and iCE40HX8K, 8000 logic cell LP-Series and HX-Series devices are available now, with the smallest package starting at $1.99 in high volume. Remaining members of the Los Angeles family are expected to be in full production by Q4 2011.