With energy efficient, ‘green’ designs devices being all the rage, embedded developers need to be asking semiconductor vendors, “How green is your MCU?” (OK, so it’s black. Work with me here.)
Ever since Intel hit the Power Wall in 2004—when the Pentium 4 drew 150W and approached 1000 pins—low-power design has come into its own. Over the past decade smart engineers have come up with a seemingly endless number of innovative tricks to stave off the frequently predicted death of Moore’s law, which was supposed to happen first at 90 nm, then 65 nm than 40 nm, etc. Still, when gate doping variations of several atoms can cause a transistor to fail, the laws of physics are finally asserting themselves. As one wit observed recently about Moore’s law, the party isn’t over but the police have arrived and the volume has been turned way down.
On one level better process technologies have gone a long way toward enabling low-power design. Smaller geometries enable lower voltage cores, which helps exponentially on the power front. Strained silicon, silicon-on-insulator, high-K metal gates and other clever process innovations have all enabled the continuing push to smaller geometries and more energy efficient designs.
On the system level design engineers have developed a long succession of power management techniques. Modern MCU’s typically rely on power gating, clock gating, and more recently dynamic (even adaptive) voltage and frequency scaling to minimize power consumption in both active and inactive modes. With the number of sleep modes and voltage islands proliferating, fine-grained power management becomes so complex that most CPUs now rely on separate power management ICs (PMICs). Since MCU’s are more self-contained, much of the power management burden is shifted from the embedded developer back to the chip designer.
Low Power –> Ultra-Low Power
If not the chips then the ‘race to the bottom’—in terms of power—between MCU vendors is getting heated. With the numbers they’re hitting, it’s hard to argue that the newest MCUs are indeed ‘ultra-low power’.
TI promotes its 16-bit RISC ‘ultra-low power’ MSP430 line in a wide range of applications, including a wireless sensor circuit that can operate from a single coin cell for up to five years (thanks in part to a very short duty cycle). The MSP430C1101—with 1kB of ROM, 128B RAM, and an analog comparator—draws 160 µA at 1 MHz/2.2V in active mode, 0.7 µA in standby mode, and 0.1 µA in off mode. This week TI announced its Grace software platform, a free plug-in for Code Composer Studio that provides a detailed graphical user interface to simplify low-level programming of MSP430 MCUs.
Microchip’s answer to the MSP430 is its eXtreme Low Power PIC Microcontrollers with XLP Technology. XLP processors include 16 to 40 MIPS PIC24 MCU & dsPIC DSC families with up to 256 KM of memory and a variety of I/O options. On its web site Microchip emphasizes how low power its devices are in deep sleep mode, comparing the PIC24F16KA102 favorably to the MSP430F2252 LPM3 at 3V. Comparing power in active modes is considerably more complex, being highly application dependent. That’s what evaluation kits are for.
Silicon Labs claims that its C8051F9xx ultra-low-power product family includes “the most power-efficient MCUs in the industry,” with both the lowest active and sleep mode power consumption (160 µA/MHz /50 nA for the C8051F90x-91x) compared to “competitive devices.” Comparing data sheets is often and exercise in “apples and oranges,” but the numbers do justify the impression that ‘ultra-low power’ is a lot more than marketing hype.
NXP is definitely into green MCUs with its GreenChip ICs that “improve energy efficiency and reduce carbon emissions.” NXP’s recently announced LPC11U00—being a Cortex-M0-based MCU—is decidedly low power, but this one focuses more on connectivity, incorporating a USB 2.0 controller, two synchronous serial port (SSP) interfaces, I2C, a USART, smart card interface3 and up to 40 GPIO pins.
STMicroelectronics features 8- and 32-bit families of ultra-low-power MCUs, apparently skipping over the 16-bit migration path that Microchip needed to fill. The 8-bit STM8L15xx CISC devices can run up to 16 MIPS at 16 MHz but still only draw 200 µA/MHz in active mode and 5.9 µA down to 400 nA in various sleep modes. Like NXP, ST is into connectivity, including a wide range of options on different devices.
Connectivity and flexibility are the main selling point for Cypress’ programmable system-on-chip or PSoC. PSoC 5 is based on a 32-bit Cortex-M3 core running up to 80 MHz. Incorporating a programmable, PLD-based logic fabric, the CY8C54 PSoC family can handle dozens of different data acquisition channels and analog inputs on every GPIO pin. The chip draws 2 mA in active mode at 6 MHz, 2 µA in sleep mode (with RTC) and 330 nA in hibernate with RAM retention.
Grill the Gurus
If after reading all the datasheets you still have questions, this Thursday you can ‘grill the gurus’ online in real time as EE times presents the Digi-Key Microcontroller Virtual Conference: New Directions in MCU Designs, from 11-6 EDT. From 11:15-12:15 EDT I’ll be moderating the panel “Low-Power Design—Keeping Hot Designs Cool,” and questions from the audience are encouraged.
From 12:30-1:30 EDT Scott Roller, Vice President and General Manager, Microcontrollers at Texas Instruments will deliver the keynote, “What Will Make The Biggest Impact: Low Power? Connectivity? Simplicity? Yes.” TI sees the market for embedded MCUs exploding over the next several years, and it’s working on some interesting innovations that should open up new markets for developers.
Throughout the day there will be series of panels, webcasts, chats and exhibits at (virtual) pavilions of interest to the embedded design community. Click here to check it out. I hope to see you there.