Collaboration Key to Future Semi Advances
If there’s any lesson to be learned from the recent evolution of the consumer electronics industry, it’s never underestimate the ability of portable system designers to find new and innovative ways to increase functionality and reduce system footprints. Today’s tiny MP3 players, 3G phones and personal navigation devices (PNDs) offer ample evidence of their skill.
But the skyrocketing costs of leading-edge semiconductor process technologies pose a formidable challenge to their future success. Moore’s Law continues to offer portable system designers the shortest path to better performance, lower power consumption and smaller product footprints. As silicon manufacturers march down the process roadmap toward 32-nm, however, the costs of moving to the next process node are spiraling out of control. Clearly, no individual semiconductor manufacturer can afford to foot the bill.
New Model Needed
What the industry needs is a new approach to semiconductor research and development that helps mitigate these escalating costs without compromising an IC designer’s ability to build complex designs in a short development cycle. As it becomes increasingly difficult for semiconductor companies to differentiate their products on the core CMOS process technology, they need a business model that will allow them to share these high development costs across a common process platform with other semiconductor manufacturers and still offer opportunities to add unique value.
Perhaps the best example of this new strategy is the Common Platform Alliance. Founded initially by Chartered Semiconductor, IBM and Samsung, the alliance has grown to eight members with the addition of NEC Electronics, Toshiba, ST Microelectronics, Infineon, Freescale and AMD. The premise behind the alliance is that while the CMOS process is still the foundation for technological advances, it is no longer a differentiating factor in itself. By sharing R&D expenses, members of the alliance can now split the prohibitively high costs of developing new process technologies at each node.
As a result, the development of a common CMOS platform gives alliance members access to leading-edge technology at a fraction of the cost and in a much shorter development cycle. For example, the Common Platform Alliance announced on 4/14/08 that it has demonstrated significant performance and power consumption advantages with its 32-nm process technology using a high-k metal gate process that will deliver up to 35 percent better performance and up to 45 percent lower power consumption than 45-nm technologies at the same operating voltage.
While that base CMOS process will no longer differentiate one semiconductor vendor from another, it can now serve as a platform for each alliance member to add its own unique functionality. By using their extensive expertise in areas such as embedded DRAM, nonvolatile memory or various low power technologies, individual semiconductor manufacturers can more quickly bring to market highly differentiated ASICs or SoCs.
Consumer demand for smaller, higher performance and more power-efficient portable products isn’t going away. But if the electronics industry wants to meet that need, semiconductor manufacturers will have to pursue new, more collaborative approaches to building high performance ICs.
NEC Electronics America
Santa Clara, CA
This article first appeared in the January, 2009 issue of Portable Design. Reprinted with permission.