Design Articles

Taming the Synchronous Buck-Switching Waveform

Synchronous buck converters are highly efficient but notoriously noisy. They don't have to be.

By Josh Mandelcorn, Member Group Technical Staff, Power Management, Texas Instruments

The synchronous buck converter achieves high efficiency by replacing the Schottky clamp diode with a low-side MOSFET. This MOSFET has a very low drop across the switch. However, because its internal diode is not a Schottky, when it turns off and the high-side MOSFET is turned on, a large ringing in the waveform occurs. This is because the low-side MOSFET needs to be completely off before the high-side MOSFET turns on to prevent cross conduction. The choke current flows briefly in the internal non-Schottky diode until the high-side MOSFET turns on. This diode builds up stored charge, which when pulled out by the high side switch, creates a large ringing. This ringing could be over twice the input voltage and is in the range of 50 100 MHz. This ringing can continue for several cycles creating system wide noise.

The large voltage overshoot requires the low-side MOSFET to have a higher voltage rating. The higher voltage rating part generally has more gate charge and a higher on resistance. This reduces the efficiency gain of the synchronous buck. The system wide noise affects the high-frequency circuitry using the power supply. Dealing with noise problems consumes a great deal of time in the product development cycle.

Below are three design tips that, when combined, will reduce system noise and voltage over shoot. This can allow the use of 25V transistors in a 12V system:

  1. Slow down the turn on of the high-side MOSFET, but not the turn off by putting a resistor in series with the “boot” capacitor;
  2. Add a snubber from switch node-to-ground with a time constant of about 1.5nsec; and
  3. Pay attention to layout. The input capacitor must bypass the main switches very closely, and the snubber must be close to the low-side MOSFET.

Advantages of lower Vds MOSFETs

New MOSFETs are always coming onto the market with lower gate charge and or lower on resistance for a given Vds voltage rating. However, the general trend has always been that for the same current carrying capability you save on die size, cost and gate charge, if you can reduce the Vds rating. For a given die size or package, reducing Vds allows a lower on resistance and higher current carrying capability.

Lower gate charge helps efficiency by reducing the power needed for the gate drive. Also, it allows rapid turn on and off from controllers with weaker gate drive capabilities without requiring an added gate drive stage. In a large volume application the ability to use a less costly controller with weak gate drive can be critical in meeting cost targets.

Slowing high-side switch turn on

The goal is to modify the high-side gate drive to reduce the stress on the low-side MOSFET. The rapid turn off of the high-side MOSFET can put stress on the high-side MOSFET drain to source. However, in practice with 12V applications this overshoot is rarely more than 7V. Also, the speed of turn off of the high-side MOSFET affects efficiency in a substantial way. On the other hand, the speed of the turn on affects the overshoot of the switch node, which can be up to 2.5 times the input voltage. Further, the speed of turn on of the high-side MOSFET has less of an effect on the efficiency. Hence, a means of slowing down the turn on and not the turn off of the high-side MOSFET is needed. The traditional approach of adding a gate drive resistor very often slows down the turn off more than the turn on.

Adding a resistor to the “boot” capacitor will slow down the turn on of the high-side FET and have minimal affect on turn off. This is because the gate drive current flows through the boot capacitor during turn on, but not during turn off.


They are used to reduce the voltage stress at a given node in a circuit. They have been around for as long as most of us. Due to their added losses designers tend to avoid them. However, it has been shown that adding a snubber can reduce overshoot for less added losses than further slowing down the gate drive turn on. Also, the snubber is the only method to rapidly dampen the 50 – 100 MHz ringing. A resistor and series capacitor connected from the switch node-to-GND is used for the synchronous buck circuit. Based upon testing, reducing the resistor value to give a time constant of about 1.0 to 1.5nsec works best for overshoot reduction and ring damping. Testing has also shown that location is key for reducing overshoot. In one set up moving the snubber from near the high-side FET to near the low-side FET reduced overshoot by 6-7 volts.

figure 1
Figure 1: Power train schematic

Figure 1 shows a tested circuit incorporating these design tips. Figure 2 shows the main waveform before adding the snubber. Figure 3 shows the same waveform after adding the snubber. Overshoot was reduced by 6V and ringing duration by about a factor of three. In another application with a load current of 16A, adding a 2200pF in series with 0.68 Ohms worked best. With switching frequency of 300 kHz added losses due to snubber are estimated to be Csnubber times VIN squared times switching frequency or 45mW in this circuit, and about 100mW in the 16A application.

Figures 2 and 3 show a major waveform before and after a snubber is added:

figure 2
Figure 2: Major waveform before turn on
slowed down and snubber added
figure 3
Figure 3: Major waveform after snubber added and gate slowed down
figure 4
Figure 4: Preferred layout of major power parts and snubber


Coupling the input capacitor very close to the low-side source and high-side drain reduces overshoot and noise radiated through the system. Even if the ringing is not suppressed with a snubber, the close coupling reduces the size of the radiating 50–100 MHz antenna. In one application with several 6V input converters and a sensitive high frequency radio, this improvement of close coupling to the input capacitors was enough to solve a serious system level noise issue. Figure 4 shows the preferred layout for the FETs, input capacitors and snubber.


Based upon test experience, the three methods shown above can “clean up” a synchronous buck converters main waveform. This can allow the use of lower voltage main switches. The “clean up” will also avoid system noise complaints and speed up final product introduction. The lower voltage FETs can improve efficiency more than the added losses due to the slower high-side turn on and added snubber.


  1. To download a datasheet for the TPS40303, visit:
  2. To download a datasheet for the CSD16232Q3, visit:
  3. Join TI’s Power Forums where you can ask questions and share knowledge on the TI E2ETM Community:

About the Author

Josh Mandelcorn’s focus is on low-power isolated and non-isolated converters at Texas Instruments where he is a Member of the Group Technical Staff. With more than 27 years of power supply/system experience, Josh has been either inventor or co-inventor of 17 US Patents. Josh received his BSEE from Carnegie-Mellon University, Pittsburgh, Pennsylvania. In 1998 he was appointed Distinguished Member of Technical Staff in Bell Labs. You can reach Josh at ti_

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