How to Make Mobile WiMax Consumer Devices a Reality
Mobile WiMAX promises a true broadband internet experience. But making it mobile isn’t easy.
With the completion of the IEEE 802.16e specification, mobile broadband service is now beginning around the world bringing fixed broadband services to homes and businesses. There are now over 75 commercial networks in operation worldwide supporting 1.3M subscribers. The bulk of these subscribers are using fixed WiMax service. To continue subscriber growth, network service providers have realized giving consumers the ability to “take the internet wherever you go” has huge potential. To do this effectively, mobile devices are needed that will mimic the internet experience at home regardless of location.
Original equipment manufactures (OEMs) have provided the first generation of mobile WiMax products including PCs, smart phones, gaming devices and ultra-mobile PCs (UMPC). Unfortunately, these devices are expensive and do not meet the battery life requirements consumers have come to expect. Given this, OEMs are challenging semiconductor manufacturers to significantly reduce price and power consumption since the underling silicon makes up a large percent of the overall system power.
Road to Low Power
Since WiMax is based on complex Orthogonal Frequency Division Multiplexing Multi-Access (OFDMA) technology, vendors have been focused on functionality, interoperability and time-to-market. This evolution is similar to cellular, wireless LAN (WLAN) and Bluetooth. All of these wireless technologies were initially expensive and power hungry, and the resulting devices were large with limited features. As standards and the market stabilized, chip companies began to focus on cost and power reductions.
The methodology employed to achieve these reductions varied depending on the company. Many would rely on the next generation semiconductor technology node along with better power management design techniques. Some would also look for processors and peripherals that were more power efficient. These techniques have clearly achieved good results, since many of today’s mobile devices have acceptable operating times.
Even so, the demand for more complex wireless systems continues to push forward. For example, while common cell phones may have acceptable battery life, smart phone batteries, under heavy use, are likely to last only one day. Or an MP3 player battery life may be fine, but add video and WLAN to it and battery life becomes a problem again. Now consider the effects of adding WiMax to these devices for a true mobile broadband experience. This new capability will continue to push all aspects of the system to reduce power.
SoC Design Methodology
Technology decisions for mobile WiMax chip designs often center on choosing a processor with the performance to meet the speed requirements while also supporting low-power features. Other component decisions include a digital signal processor (DSP) to support real-time algorithm processing, input and output (I/O) devices and the size and types of on-chip memory. Along with choosing system components, architecture decisions need to be made about which functions will be implemented in software vs. hardware. These choices significantly influence the power, performance and overall cost of the system. From a business and application point of view, decisions need to be made to determine if the SoC will support other wireless protocols that could include WLAN, GSM, CDMA, Bluetooth and/or GPS. Any combination of these wireless technologies is possible, but adds significant complexity to the overall system design.
Figure 1: Typical WiMax SoC with additional Wireless Protocol
A typical embedded WiMax SoC block diagram is shown in Figure 1 (Note: the diagram has been simplified focusing only on the issues concerning power). In this configuration, the system memory is shared between the processing elements [although many systems use tightly coupled memory (TCM)] and each MAC has control of the system resources and peripherals. Much care is typically taken in selecting individual blocks to be power-efficient. However, the final chip performance may not meet the intended power consumption targets due to the interaction between the processor blocks and the memory.
In current SoC designs the CPU(s) controls the data flow and the interaction with memory and peripherals. Since the design is ‘CPU centric’ the processor is frequently in an active state which utilizes the most power. In addition to the control issue, the system has multiple processing elements that are competing for resources including access to memory and peripherals. With traditional bus architectures, bandwidth is limited with the potential for long latency. Given this, the processor(s) will often waste cycles due to bus conflicts and waiting for data that will again leave the processor in an active state longer than necessary.
Maximize Processor Efficiency
Figure 2: WiMax SoC with a Micronetwork
Building on many of the existing system-level power-saving techniques, an alternative “interconnect-centric” SoC architecture enables a significant reduction in overall power. This methodology starts from the view of the interconnect and builds out. Using a ‘micronetwork’ (Figure 2) allows the SoC designers to model the interaction between all processing elements in order to optimize data flow and processing efficiency while also applying power-saving techniques across the entire SoC.
In addition to other advantages, the creation of a micronetwork offers many system advantages from the perspective of power consumption.
Advanced Interconnect Architecture
A micronetwork provides an advanced interconnect fabric along with data flow services. Efficiency is improved by adding new flow control services to the SoC. For example the micronetwork can support functions that include quality of service (QoS) to set data priorities, firewalls to protect regions in memory, error handling, data width conversions and power management. These new data flow services allow the CPU(s) to become a facilitator thus improving its overall efficiency which will have the effect of allowing it to remain in a low-power state for longer periods of time.
Many micronetworks support a non-blocking architecture along with multi-threading capability. A non-blocking transaction model offers the advantage of servicing requests from multiple processors at the same time with minimal latency in the response (versus a blocking transaction model that services one processor at a time). Multi-threading offers the advantage of splitting processes into logic threads in order to improve the overall processing efficiency (e.g. real-time functions in one thread and channel information in another).
WiMax SoCs can take full advantage of this architecture given that there are multiple processors, often with high bursts of data traffic. This is especially true for SoCs that have multiple wireless protocol MACs on a single chip. In this situation, non-blocking capability simplifies the data flow since each processor will have predicable bandwidth that will minimize the number of cycles wasted waiting for system resources. As in any wireless system the goal is to process the data quickly and return to low-power mode. This improvement in duty cycle will contribute to the reduction in average power consumption of the SoC.
These processor efficiency improvements become even more significant as the amount of data to be processed increases. For typical CPU and cache configurations reductions in instructions cycles of fifteen percent have been shown in simulations for processing large amounts of data (i.e. time waiting for data after a cache miss with non-blocking versus blocking). Having a non-blocking architecture will be a key performance advantage for mobile WiMax devices that have video processing capability.
The gain in processor bandwidth can have other positive impacts on the system. It is certainly possible to reduce the clock speed of the processor thus lowering the active power consumption. As mentioned previously, it is typically better to process the data as quickly as possible and return to low power mode. This is a trade-off that needs to be evaluated based on the specific application requirements. The gain of processing power in the MAC can allow the system software designer the flexibility of adding new functions to the MAC. These functions may have previously been done by the applications processor or other hardware. Integrating as many functions as possible into the MAC has the advantage of a ‘zero load’ architecture for the applications processor. This will save overall system power since the applications processor will be able to remain in low-power mode during data processing and not have to share the work load with the MAC.
Designing with an interconnect-centric architecture also can allow for decoupling of each processor and peripheral from the system. With decoupling, the interconnect acts as a buffer between the system components, thus enabling independent clock control and voltage levels to each section of the chip. Clocks and power can be removed from sections of the SoC for maximum power saving when that portion of the chip is not in use. The interconnect works in conjunction with an external power unit to enable features such as auto-wakeup, rapid power-on and power-off. Fast wakeup and power-down times would be difficult to achieve if implemented by the CPU due to long instruction cycle delays.
The need for mobile broadband services is pushing mobile devices to the limit in terms of processing power and battery life. Innovative techniques and architectures that drive reduction in power consumption for mobile WiMax devices are now required as the market has reached a maturity level that warrants these efficiency gains. A design methodology that centers on the interconnect allows SoC designers to look at the overall system from a data flow perspective in order to maximize processor efficiency, minimize latency and improve overall system power control.
This article originally appeared in the January, 2008 issue of Portable Design. Reprinted with permission.
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