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Design Articles

Processor Energy Savings Through Adaptive Voltage Scaling

AVS utilizes closed-loop control and configurable gains to achieve maximum system energy efficiency

By Mark Hartman, Applications Engineering Manager, National Semiconductor’s Advanced Power Group

Frequency and voltage scaling are common place in portable electronic processors. These devices are providing more and more functionality and demand the highest data processing efficiency. Adaptive Voltage Scaling (AVS) provides the lowest operation voltage for a given processing frequency by utilizing a closed loop approach. The AVS loop regulates processor performance by automatically adjusting the output voltage of the power supply to compensate for process and temperature variation in the processor. In addition, the AVS loop trims out power supply tolerance. When compared to open loop voltage scaling solutions like Dynamic Voltage Scaling (DVS), AVS uses up to 45% less energy (Figure 1).

figure 1
Figure 1: Comparison of fixed voltage, DVS, and AVS energy savings
in a processor

AVS is a system level scheme that has components in both the processor and power supply. The Advanced Power Controller (APC) provides the AVS loop control and resides on the processor. The Slave Power Controller (SPC) resides on the power supply and interprets commands from the APC. The IP provided in the APC and SPC automatically handle the handshaking involved in frequency and voltage scaling, simplifying system integration in the application.

AVS uses a novel closed loop approach to voltage scaling. The AVS loop is closed around the performance of the processor, eliminating any excess voltage margin. This is in contrast to table-based DVS systems, which must include extra voltage margin. The AVS loop also provides the ultimate kelvin sense connection for the voltage regulator feedback by actually sensing the voltage in the load. This eliminates voltage error due the ground difference between the power supply and the processor. The power supply tolerance is also trimmed out automatically by the AVS loop, further reducing the margin voltage. All these reductions in the supply voltage yield a dramatic energy savings in the processor because the dynamic energy usage is proportional to the voltage squared.

The Processing Engine

figure 2
Figure 2: The Adaptive Voltage Scaling (AVS) loop and its components

The key blocks in the system are illustrated in Figure 2. The Advanced Power Controller (APC), licensed by National Semiconductor, provides the AVS loop control and all voltage/frequency scaling handshaking. The PowerWise Interface (PWI) is an open standard interface. This 2 wire, serial interface provides the necessary bandwidth and protocols for AVS. Finally, the Energy Management Unit (EMU) provides the voltage scaling and regulation.

The APC handles all aspects of voltage control, and has the ability to actively minimize the power consumption of the host processor. It is realized in synthesizable RTL and has the following functional components:

  • Hardware Performance Monitor (HPM)
  • Digital loop filter and
  • PowerWise Interface (PWI) master module.

These elements work together to allow simple and accurate voltage control from the external power supply.

The hardware performance monitor (HPM) and digital loop filter are used in AVS to measure the performance of the digital circuit for a given operating performance requirement. The measurement data from the HPM is processed in the digital loop filter and sent to the PWI master to output a voltage request to the power supply.
           
In the closed loop AVS system, there exists both continuous time (power supply) and discrete time (HPM, discrete compensation) elements. Therefore, sampled-data theory can be used to analyze the system. The HPM outputs a digital word and has as its input both desired performance (clock frequency) and analog voltage. This digital word is a relative measurement of the silicon performance. The sampled-data control loop attempts to regulate this measured output to the reference input, which is also a digital word. The loop stability will be determined by the discrete-time compensation, which can be implemented any number of ways.

Power savings is further optimized by partitioning the SoC design into several independent voltage domains. For example, the processor may have a core and a hardware accelerator that operate on different scaling voltage domains. The APC 2.0 enables control of multiple AVS domains, commonly needed in state-of-the-art SoC design. The APC 2.0 can accommodate up to 16 slaves over the PWI 2.0.

The PWI is an open standard interface where the serial data is transferred through the SCLK and SDAT pins. Data transfer rate up to 15 MHz fulfills the bandwidth needs of closed loop AVS. This bandwidth is necessary and must be guaranteed by the interface so that the loop can operate without too much lag.

The last component to the AVS loop is the Energy Management Unit (EMU). The EMU provides stable voltage scaling and regulation to the processor core(s), as well as supporting voltages such as the PLL and logic supplies. To operate in the AVS loop, the EMU must contain the Slave Power Controller (SPC), which interprets the PWI commands. The EMU specifications will effect the AVS loop performance. Just as it is essential for the PWI to provide bandwidth, the EMU must also satisfy bandwidth requirements.

AVS not only provides great energy savings, but also simplifies system integration. The AVS loop operates autonomous to the processor and requires no software intervention, except for a few one time configuration settings. In addition, the APC has a voltage monitor that senses when the voltage is settled to the appropriate level for a given target operating frequency, simplifying the handshaking that occurs between voltage and frequency scaling.

Frequency and Voltage Scaling

A review of frequency and voltage scaling will aid in understanding the key benefits of AVS. The basic idea is to scale the frequency to the work load demanded of the processor, and in turn scale the voltage to the minimum required to operate at the current frequency. The benefit of doing this is that the dynamic (switching) energy used for a given process (measured in processor clock cycles) is proportional to the square of the supply voltage. For example, 100 clock cycles at 1.2 V uses more energy than 100 clock cycles at 0.9 V, regardless of the operating frequency. In any frequency/voltage scaling system, there are two transitions that can occur: a rising and falling frequency/voltage scaling event.

A rising frequency/voltage scaling event begins with a request for a higher operation frequency by some work load monitor. To support this higher operating frequency, the system must first increase the supply voltage via some method (AVS and DVS are two examples). After the voltage has settled to its new, higher value, the system engages the requested higher frequency operating clock.

Likewise, a falling frequency/voltage scaling event begins with a request for a lower operation frequency. However, in this case the supply voltage is already high enough to support the lower frequency, and the operating clock is immediately reduced. Now the system reduces the supply voltage in order to match what the new, lower operating frequency needs. One important difference in a falling frequency/voltage scaling event is that any undershoot in the supply voltage transient must be accounted for as extra margin in the system (see Figure 3). Therefore it is desirable to eliminate undershoot.

Closing the Loop

figure 3
Figure 3: Undershoots increase voltage margin

The AVS system achieves accurate and controlled voltage scaling by using a configurable feedback loop with the power supply. By changing the reference, one can change the amount of voltage margin at a particular operating frequency. By changing the loop gain, one can change the slew rate of the voltage scaling events. The AVS loop even distinguishes between rising and falling voltage scaling events so that different gains and thus different slew rates are applied. This allows one to minimize undershoot on a falling transition while minimizing rise time on a rising transition. Recall that minimizing undershoot directly translates to reduced supply voltages and energy usage. This and other means of flexibility are built in to the APC.

The AVS loop is a true closed loop system, and only requires a few parameters to be configured. Just like any feedback system, the loop must be compensated to provide a stable response. The APC has registers that set the gain of the loop. The gain must be set high enough to provide adequate rise and fall times, but low enough to guarantee an overdamped response (no over- or under-shoots). This is a straight forward exercise since we are only affecting the gain of the loop, and can be done on a bench or through the equations provided in the APC IP documentation.

Besides setting the gain of the loop, the reference must also be set. The reference to the AVS loop is a digital word that corresponds to the desired processor performance, as measured by the HPM. Essentially, this is like regulating the delay margin in a setup time spec. Since the loop is directly regulating the processor performance, any amount of desired margin can be programmed. This gives flexibility to go from an aggressive, optimal efficiency design to a conservative, less efficient design. By setting the AVS loop gain and reference, the loop will automatically handle voltage scaling.

Monitoring Voltage

An important but not often mentioned feature of the APC is the voltage monitor. The voltage monitor greatly simplifies voltage and frequency scaling by providing a ‘power good’ flag for every voltage scaling event that occurs. This is particularly important when scaling to a higher voltage/frequency. The new, higher frequency can not be engaged until the voltage rises to support the shorter delay times. The voltage monitor allows the processor to switch to the new, higher clock frequency as soon as the voltage has settled to its new, higher value. This not only allows the system to run faster, but also eliminates the need to characterize the power supply rise and fall times, which vary with component tolerances.

The voltage monitor enables the system to scale voltage at a faster rate since the exact time the voltage has settled is known. This in turn allows the system to scale between frequencies at a higher rate, and increase system efficiency by spending less time at higher voltages.

The AVS system offers optimal voltage scaling for a given processor. By virtue of closed loop performance regulation, the lowest voltage for a given operation condition is always selected. The gain of the loop can be configured for both rising and falling voltage scaling events, further reducing margin needed for undershoots. The voltage monitor contained in the APC further reduces system integration complexity by providing an indicator that the voltage has settled to its new value. This provides an automatic handshaking between voltage scaling and frequency scaling. Through closed loop control and configurable gains, the maximum system energy efficiency is achieved.

National Semiconductor Corporation
Santa Clara, CA
(408) 721-5000
www.nsc.com

This article originally appeared in the March, 2008 issue of Portable Design. Reprinted with permission.

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