Image
image
image
image


Design Articles

Lower Supply Voltages Enable Low-Power Portable Electronic Devices

Few power management methods will help your energy budget more than dropping the supply voltage. But doing so while maintaining clock frequency and signal integrity is no easy trick.

By Aditya Rao, Product Marketing Engineer, Memory Products Division, Microchip Technology Inc.

cell phones

The tremendous growth in the semiconductor industry over the last two decades has largely been a result of the scaling of CMOS devices which, over the years, has yielded lower costs with more die per wafer, smaller feature sizes and increased performance. However, device scaling has reached a point of threshold today, wherein its benefits are realized only if a device’s power consumption can be reduced by a few orders of magnitude.

Power minimization is of paramount importance for designers today, especially in the portable electronic-device market, where devices have become increasingly feature rich and power hungry.   Low supply voltages play a significant role in determining the power consumption in portable electronic-device circuits.

This article will examine the benefits of low voltage within portable electronic designs, showing how the advantages of low-power can be achieved. 

An electronic device’s overall power consumption can be represented by:


PTOT=αCTOTVDD2f +VDDIOFF; where IOFF=Ioe(-qVTH/nkT)

Equation 1: An Electronic Device’s Overall Power Consumption


The first term in Equation 1 represents dynamic or “switching” power, while the second term represents static power—primarily due to leakage currents. (The short-circuit power, which forms less than 5% of the total power, is not included.)  As a result of scaling over the years, the dynamic power has remained almost constant (see Figure 1), so increases in switching frequency (α), clock frequency (f) and total capacitance (CTOT) have been largely offset by the supply voltage (VDD). figure 1
Figure 1: Dynamic and Static Power Consumption With Technology Scaling

The paradox faced by designers is that a reduction in supply voltage helps to reduce power but, on the flipside, it limits the clock frequency.  Additionally, a reduction in supply voltage reduces the saturation current through the MOSFET, thereby cutting speed and performance.  Hence, the supply voltage plays an important role in the speed vs. power tradeoff. 

To counter this reduction in saturation current, threshold voltage (VTH) has also scaled down.  This has led to a tremendous surge in sub-threshold leakage current (IOFF) and static power, especially in the deep submicron process technologies (see Figure 1).  Minimizing this is expected to be a significant challenge for future low-power designs. Table 1 shows the effect of scaling on various parameters.

Today's consumer-electronics market is driven by battery-operated, wireless applications and portable devices that are becoming increasingly sophisticated.  All of this has created a huge demand for longer battery life.  As a result, design practices today are increasingly focusing on the demands and requirements of the end application and target markets, rather than just overall system optimization, for better performance.  In fact, to achieve this, foundries nowadays offer multiple options on threshold voltage, supply voltage and oxide thickness for the same process, providing designers with the flexibility to choose the best device for helping them overcome some of the limitations of power-performance tradeoffs, enabling them to tailor designs to the needs of the end application.  For example, portable applications which place a higher premium on power consumption are often designed using higher VTH transistors, trading off performance for lower power.  On the other hand, fast switching circuits will use low VTH cells.

table 1
Table 1: The Impact of Scaling On Device Parameters

There are many methods that designers can employ to reduce power consumption in portable electronic devices.  One is known as clock gating (see Figure 2b). Clock power is an important component of overall dynamic power.  One way to reduce clock power is to use clock gating, which dynamically disables the clock in unused parts of the circuit.  This avoids the unnecessary power dissipation caused by charging and discharging the clock signal at these unused gates.  Gating is generally achieved by ANDing the clock signal with a clock-gate signal, which rises whenever the part of the circuit that needs to be gated is active and remains low otherwise.  Many synthesis tools offer clock-gating insertions at the RTL level. 

Another commonly used technique is power gating (see Figure 2a), which uses high threshold-voltage transistors or sleep transistors in circuit blocks that switch infrequently.  This results in zero standby currents during the inactive state.

figure 2
Figure 2: (a) Power Gating Using Sleep Transistors and (b) Clock Gating
Dynamic supply-voltage scaling is another method employed that often used in low-power designs to efficiently tackle the power/performance trade-off.  The underlying principle is to scale the supply voltage down along non-critical timing paths, thereby lowering the overall dynamic power consumption.  However, along timing-critical paths, the supply voltage is kept at its nominal value to ensure timing closure.  It must also be noted that the additional voltage levels and their integration into the design increase the overall cost of the design.  Modifications involve adaptive supply-voltage scaling, based upon the sub-circuit workload.

Next, dynamic threshold-voltage scaling can be used, where the threshold voltage of cells is increased by controlling the substrate biasing.  A larger threshold voltage implies reduced passive leakage, thus shrinking the static power consumption. Therefore, choosing supply-voltage or threshold-voltage scaling depends upon whether dynamic or static power dominates the power equation. 

Architectural optimizations implemented during the RTL and synthesis phases of the design flow are critical as key design tradeoffs are made in this phase.  Mapping and sizing techniques are often used on the netlist to find the high switching inputs.  These are then mapped to low-capacitance inputs.  If possible, pipelining techniques should be implemented to further save power.

Scaling to the deep sub-micron level has opened the door to a number of second-order effects, such as tunneling, channel-length modulation, punch through, drain-induced barrier lowering and velocity saturation.  All of these effects further impact both power consumption and performance, making designs increasingly complicated and causing a growing need for newer, more innovative materials and processes.  For example, the use of High-K dielectrics helps mitigate the effects of tunneling with thicker gate oxides. Strained-Si helps improve mobility, which mitigates the effects of velocity saturation and allows for higher threshold voltages for the same “on” current.  This reduces static power. Table 2 shows the list of proposed new materials and their respective advantages.

table 2
Table 2: New Device Materials and Their Advantages

Signal Integrity (SI) has become a major concern today, especially in deep sub-micron processes.  Lower noise margins with supply-voltage scaling have meant more stringent restrictions on the signal output and quality.  This is particularly demanding with faster rise times and increased slew.  SI issues creep in not only when data that is latched is incorrect, but also when data that needs to be latched doesn’t arrive at the right time.  Substrate coupling, crosstalk and circuit interconnects are the primary culprits for SI problems. 

Some tips and tricks for overcoming these SI problems include:

  1. Use differential signals at high fanout nodes.
  2. Use ECL signals for clocking.
  3. Use parasitic extraction tools that model 3D parasitics and inductance, especially in high-frequency designs. This increases the accuracy of the slew-rate prediction. 
  4. Model capacitors as nodal capacitors, as opposed to capacitors to ground.
  5. Match impedance at the package boundary.
  6. Use decoupling capacitors between the supply voltage and ground at the external pins.
  7. Limiting di/dt helps reduce crosstalk and ground bounce.
  8. Optimize layout for fewer metal layers and minimum wire length.
  9. Give greater margins during design to allow for costly post-silicon SI defects.

Non-Volatile Memory Technologies

The non-volatile memory market, consisting primarily of Flash and serial EEPROM, is one of the fastest growing in the semiconductor industry.  EEPROM devices are particularly useful in portable and consumer-electronic applications, providing system programmability and data storage.  They also find applications in power-down storage; error diagnostics; secure data storage; maintenance logs and configuration storage; and often as look-up tables and analog controls in consumer-electronic applications. What makes serial EEPROM attractive is its high endurance, low cost, byte-level programmability and low power.  These attributes make it ideal for portable consumer-electronic applications, such as MP3 players, camcorders and wireless Bluetooth applications (see Table 3).  
table 3
Table 3: Application and Usage of Serial EEPROM Devices, By Density

Serial EEPROM devices are becoming increasingly power savvy.  Leading providers of EEPROM devices today specify EEPROM devices with typical standby currents of around 0.01 micro Amperes (μA).  In fact, newer serial EEPROM parts effectively tackle the speed-power trade offs as well.  For example, the 1 Mbit 25AA1024 or 25LC1024 (25XX1024) serial EEPROM devices from Microchip Technology are not only the fastest (20 MHz) 1 Mbit SPI serial EEPROMs available, but they also have a deep power-down mode feature that helps to reduce power consumption.  These additional low-power features makes these devices well-suited for low-power designs up to around the 1 Mbit density level. (Serial Flash memory devices typically have standby currents around 15 μA at this high-end density.)

Floating-Gate Design Challenges

Portable applications, with their scaling of other on-board chip components, have forced serial EEPROM devices to operate over a wide voltage range, typically 1.8V to 5.5V.  The real challenge is to ensure fast access and erase times, along with reduced write times at low supply voltages, while reducing power consumption at higher supply voltages.  An additional critical design consideration is to ensure that standby current is as low as possible, especially in battery-operated devices. 

One great advantage of non-volatile memory is that a Flash or serial EEPROM device’s power supply can be shut down to ensure zero memory leakage when not in use. When operating at lower supply voltages, write times in these devices increase dramatically.  Hence, charge-pump designs are critical in obtaining write-time optimizations.  The big challenge here is to obtain the highest internally generated write voltage at the lowest possible supply voltage, to ensure faster write times. 

Another significant challenge associated with technology scaling in floating-gate designs has to do with thinner oxides, resulting in poor write quality.  This causes lower endurance and severely affects data retention.  Also, writes are generally performed at high voltages (greater than ± 10V) making the thinner gate oxides more vulnerable to permanent oxide damage and charge loss. This severely affects reliability.

Using materials with high dielectric constants for the oxide is one way to reduce the impact of dielectric scaling. To optimize the time taken to read from floating gate non-volatile memories, the address decoding times must be optimized. The real challenge here is that at low supply voltages, the on currents are extremely low, making current sensing challenging and slow.  Boosting the voltage on the word line to obtain higher on currents is one way to work around this problem. 

On the other side of the spectrum, scaling has helped reduce the cost per bit, with reduced die sizes and cost.  It has also helped reduce power consumption, and has made these devices significantly faster with every generation of scaling. Today, low supply-voltage operation is inevitable.  The conundrum facing designers with serial EEPROMs is that having low power is useful in applications such as smart cards and DRAM modules. However, higher performance and faster access times are required when used with embedded applications and microcontrollers.  Going forward, supply-voltage limitations with smaller gate lengths are expected to lead to smaller EEPROM supply-voltage ranges.

Using lower supply voltages to help reduce dynamic power is inevitable with scaling. However, the resulting increased static power is expected to pose the biggest challenge for low-power portable designs in the future. To offset the slowdown in scaling, newer, more innovative materials like Silicon-on-Insulator (SOI) are being used to make devices more robust.  Additionally, advanced packing technology is quickly integrating into designs, with flip-chip technology becoming increasingly popular.  More sophisticated testing methodologies and EDA tools are helping designers to model systems better, thereby reducing turnaround times and costs. 

Thus, while scaling may not keep the same pace going forward, better systems, improved tools, increased used of software and architectural optimizations, newer materials and improved processes can bring the benefits of lower cost, increased performance and lower power.

Microchip Technology Inc.
Chandler, AZ
(480) 792-7200
www.microchip.com

This article originally appeared in the January, 2008 issue of Portable Design. Reprinted with permission.

 Share
Digg Reddit Del.icio.us Stumble Upon Facebook Twitter Google BlinkList Technorati Mixx Windows Live Bookmark MySpace Yahoo Bookmarks Diigo


Insert your comment

Author Name(required):

Author Web Site:

Author email address(required):

Comment(required):

Please Introduce Secure Code:


image
image