Ultra-Low Power Requires MCMM
The key to getting the most from advanced low-power designs is using concurrent analysis and optimization of timing, power and SI interactions across all the different modes and corners. The key to success is multi-corner, multi-mode (MCMM) design closure.
ICs for smart phones, music players, and other portable products now depend on a palette of relatively exotic design methods, including multiple voltage domains, and dynamic voltage and frequency scaling (DVFS), to effectively manage power. These new techniques present a minefield of challenges to the entire design flow.
The established low-power design techniques, such as clock gating for reducing dynamic power and multiple voltage thresholds (multi-VT) to decrease leakage current, are supported by existing tools for very limited mode/corner scenarios. However, designers are running into difficulty with more advanced techniques such as designing for power in a multi-corner, multi-mode (MCMM) context, multi-voltage flows, and designing power-efficient clock trees. Having the right implementation tools can make the difference between taping out on time and within spec, or facing the dire consequences of a late or underperforming product.
This article outlines the challenges of designing ultra-low power portable designs. It describes tool capabilities that designers need to avoid excessive design margins and numerous lengthy iterations. It also describes results that are being achieved today by designers working on the most advanced SoC designs at 45nm.
Managing Power Requirements
Some of the biggest design challenges are in managing both power and timing concurrently since they could potentially have conflicting requirements. The increase in the number of modes and corners, variability models, and extremely large design sizes further exacerbate the problem. Conflicting and increasing power/mode/corner scenarios result in increased iterations and longer time to closure. Take, for example, a portable device SoC as shown in Figure 1. Each functional mode—phone, MP3, GPS, camera, etc.—needs to be analyzed and optimized for specific process corners and has different leakage and dynamic power profiles.
Figure 1: A sample portable device with multiple functions, each with different power states and process variations that must be considered concurrently during physical implementation.
The traditional methods for meeting timing and power requirements, such as adding margins, no longer work at advanced process nodes. The reason is that adding margins reduces performance and adds area—two main reasons for migrating to advanced nodes in the first place. To be competitive, designers need all the benefits of advanced design and manufacturing capabilities, and the physical implementation tools must facilitate, not hinder, the process.
Complex low power designs call for new capabilities in implementation tools, including full support for multiple voltage design styles, low-power clock tree synthesis (CTS), large capacity, fast turnaround time, and accurate results that minimize or eliminate closure iterations.
However, the key to getting the most from advanced low-power designs is using concurrent analysis and optimization of timing, power and SI interactions across all the different modes and corners, a process referred to as MCMM design closure. Not all MCMM technologies are equal, though. Some tools use the concepts of ‘super-mode and ‘super-corner’, which usually implies a merging of constraints and can be inaccurate and error prone. Other MCMM solutions actually analyze multiple corner/mode scenarios sequentially, not concurrently, and run into runtime and capacity problems when the iterations between the scenarios fail to converge.
The technology to look for in a place and route solution is the ability of the core analysis data structures to represent the complex interactions between power, timing, signal integrity (SI) and area across all modes and corners simultaneously. To do this, the core timing engine would need to represent the timing graphs of all mode/power/corner combinations in a complete but compact data structure, as illustrated in Figure 2.
Figure 2: A true MCMM timing system, like that in Mentor Graphics Olympus-SoC, works with a single representation of any number of timing scenarios. This single, compact representation is not a merging of individual constraints files, so does not compromise on accuracy.
MCMM analysis must drive all implementation steps, including power-aware floor-planning, placement, MCMM-CTS, routing, and optimization. All of these components must work seamlessly and concurrently from a common database to be able to drive to design closure quickly and accurately.
Multi-voltage design with MCMM
An increasingly common technique to reduce dynamic power is the use of multiple voltage islands (domains), which allows some blocks to use lower supply voltages than others, or to be completely shut off for certain modes of operation. This presents new challenges in physical design.
Because each different voltage supply and operational mode implies different timing and power constraints on the design, multi-voltage methodologies cause the number of design corners to increase exponentially with the addition of each domain or voltage island. DVFS further complicates matters because varying frequency and clock combinations leads to even more design modes and corners. Additionally, the worst case power corners don’t necessarily correspond to the worst case timing, so it’s critical to know how to pick a set of corners that will result in true optimization across all design objectives without excessive design margins.
A true multi-voltage MCMM (MV-MCMM) implementation solution like the Mentor Graphics Olympus-SoC system shown in Figure 3, includes significant architectural and algorithmic enhancements to the traditional place and route systems to implement the high-performance low-power designs found in portable devices.
Figure 3: Physical design flow for multi-voltage designs includes the ability
to define power domains in Unified Power Format (UPF), and advanced
features for placing and routing across domains, and optimizing clock trees
for all operating modes.
In order to effectively close multi-voltage designs, both timing and power must be concurrently analyzed and optimized simultaneously for different combinations of library models, voltages, and interconnect (RC) corners. In essence, true and concurrent MCMM analysis and optimization is a pre-requisite for any portable design that uses multiple voltage domains. Anything less would not guarantee convergence because optimization in one scenario could create a new violation in a different scenario, leading to multiple iterations, unpredictable ECO loops, poor quality of results (QoR), and possibly reduce yield.
Results and Examples
Using a good MCMM place and route system can reduce design closure times by 2-3X , and save up to 30% in the power usage versus traditional solutions. MCMM is particularly valuable in synthesizing and optimizing clock trees. Power-aware CTS with smart clock gate placement, slew shaping, register clumping and concurrent MCMM optimization ensures a balanced clock tree with the minimum number of clock buffers. The experiences of designers using MCMM CTS show significant reduction in area, number of buffers, skew, total negative slack (TNS) and worst negative slack (WNS), in addition to lower dynamic power. The example in Figure 4 is actual customer data showing how a single-corner CTS implementation compares with a 9-corner CTS implementation for a 9-corner design.
Figure 4: CTS with Mentor Graphics Olympus-SoC — MCMM vs. single-corner. Complex clock trees show significant improvement in skew, number of buffers, area, total negative slack (TNS), and worst negative slack (WNS) with a native MCMM strategy.
Another real-world case, a 45nm wireless chip with four power domains, shaved the leakage power by 22% by using MCMM CTS rather than the traditional best/worst case CTS. These examples illustrate that significant power savings in advanced portable ICs come not just from the high-level architectural decisions, but from the quality of the implementation system deployed.
In the competitive market of portable electronics, designers need every edge to get to market on time with the best performance and lowest power. IC design teams should be able use all the techniques available, from multi-Vt, to clock gating, to multiple power domains and DVFS. To do so, they must make sure their design tools can support these techniques with tape-out proven, high-capacity MV-MCMM analysis and optimization.
Arvind Narayanan is a Product Marketing Manager at Mentor. He holds a Masters in Electrical Engineering from Mississippi State University and a Masters in Business Administration from Duke University. He has held various design, application engineering and marketing positions and has been very active in the UPF initiative.
Sudhakar Jilla is the marketing director at Mentor Graphics. Over the past 15 years, he has held various application engineering, marketing, and management roles in the EDA industry. He holds a Bachelors degree in Electronics and Communications from University of Mysore, a Master's degree in Electrical Engineering from the University of Hawaii, and a MBA from the Leavey School of Business, Santa Clara University.
Mentor Graphics Corporation