Supporting Next-Generation Ethernet in the Green Data Center
Implementing a superset of the the IEEE 802.3az Energy Efficient Ethernet standard for data centers could save as much as $450 million a year in the U.S.--not to mention a few trees.
As enterprise data centers expand to support cloud-based services, network managers are faced with an uncomfortable paradox: Exponential growth of users demanding high-bandwidth service is driving architectures that offer unprecedented density of 100-Mbit and 1-Gbit ports in a single line card, even as power costs and green initiatives place new demands for energy efficiency in the data center.
While some power-saving improvements can be implemented at the level of the enterprise LAN, the biggest opportunity for cutting overall power dissipation in the data center resides in the semiconductors comprising the Ethernet interface. Optimizing these chips can offer benefits in overall network node size, port density, and system power dissipation. Those power savings often are dominated by the efficient operation of the physical-layer chip, which often consumes more power than a MAC, switch, or bridge IC, particularly at 100-Mbit/sec and 1-Gbit/sec speeds, due to its active transmit and receive operations.
The efforts to conserve power at the device level are guided by standards defined by federal agencies and industry standard bodies. The drive to conserve power in network equipment took its lead from the Environmental Protection Agency’s EnergyStar program, which is actively defining certification standards for manufacturers designing IT and network equipment for the home and small business. For a variety of networking appliances and products, the EnergyStar criteria include specifications written by the IEEE, known as 802.3az Energy Efficient Ethernet, which specify (in part) how physical-layer Ethernet chips move into sleep modes.
The 802.3az effort was begun in 2007 in order to standardize concepts for a low-power indicator signal, which would be sent in the network telling the transmit circuits in physical-layer chips to shut down. A study from Lawrence Berkeley Labs, conducted in conjunction with the early work of the 802.3az task force, suggested that implementation of the physical-layer standard throughout the industry could save as much as $450 million a year in the U.S. -- $200 million from homes, $170 million from small offices, and $80 million from data centers. The 802.3az standard was ratified in October 2010.
Some companies working with IEEE have advocated a superset of energy-saving approaches to assist in making more power-efficient “green” networks, providing support for automatic link status monitoring, shutting off links which are not active; and adaptively changes power according to cable length. Vitesse Semiconductor, for example, offers status monitoring as ActiPHY, and adaptive cable-length adjustment as PerfectReach.
In addition to enabling its customers to meet EnergyStar requirements, Vitesse introduced advanced physical-layer capabilities such as continuous temperature monitoring, direct control of fans used in system-level switches and routers, and fine-grained control of LED brightness, to further improve power management in networking systems. Vitesse introduced many such features in what it called its Eco Ethernet 2 suite, in 2010.
The pressure is on semiconductor companies to move power-reducing feature sets beyond the realm of 1-Gbit/sec physical-layer devices. Because energy-saving requirements are greatest in the densest and fastest ports, OEMs and network managers alike are clamoring for advanced features in high-speed Ethernet devices. We can expect to see the first intelligent power-down 10_-Gbit/sec devices arrive in the near future. While some vendors offer what is called “subset PHY,” in which 10-Gbit links are slowed down to 1-Gbit performance when not in use, an optimal solution would provide 10G Ethernet with similar true power-down methods as currently offered in Gigabit Ethernet.
While home and small-business users have only limited opportunities to optimize power on a system level, data-center users can augment greater capabilities at the chip level by studying ways to optimally power-down entire subnetworks of servers and storage devices. Symantec, for example, re-configured its data centers for optimal traffic patterns, and was able to eliminate several terabytes of storage while completely eliminating some geographical locations of data centers. The IT and telecommunication industries are attempting to standardize these efforts through the GreenTouch and Green Grid programs.
GreenTouch was founded in 2009 by several academic institutions and corporations, and has grown to include more than 45 members. The ambitious goal is to improve the network energy efficiency of IT appliances and network nodes by a factor of 1000 by 2015. Green Grid takes its name from the smart energy grid concepts promoted by the US Department of Energy, but instead is focused on the corporate data center. Several computing OEMs, power supply specialists, and semiconductor companies belong to the consortium, though Green Grid has yet to set quantifiable targets for how it will measure data center power efficiency gains. In its first three years of existence, Green Grid has functions more as an information-sharing consortium than a standards-setting body.
Top-down efforts such as GreenTouch and Green Grid, intended to improve topology and usage planning for the data center, are to be commended for getting network managers to think proactively about how they add capacity and services. But they must be enabled from the bottom up by chip-level technologies that reduce power dissipation for all devices on the network interface card or line card.
The physical-layer device will remain the centerpiece of such efforts, as new standards efforts and new proprietary design techniques seek to keep power at an absolute minimum, even as port speeds move to 10, 40, and 100 Gbits/sec and beyond.
About the Author
Brian Jaroszewski, senior product marketing manager for Vitesse, has experience in the communications, semiconductor and financial industries. Mr. Jaroszewski has held various sales and marketing positions at Advanced Micro Devices, Legerity (now Zarlink) and Vitesse. His experience in the semiconductor industry includes a variety of technology areas, including flash memory, microprocessors, telephony, programmable logic and Ethernet networking. As Senior Product Marketing Manager for Vitesse, Mr. Jaroszewski is responsible for IP licensing business development and marketing management of the Ethernet product line for Gigabit Ethernet products and technologies. Mr. Jaroszewski holds a Bachelor of Science degree in Computer and Electrical Engineering from Purdue University and a Masters in Business Administration from London Business School.