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White Papers


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Designing Low-Power Embedded Systems, Part 1
By mastering the relationship between active power consumption, standby power consumption and the duty cycle, you can develop higher performance and more energy-efficient embedded systems that stretch the limits of portable applications. Divided into two parts, the first part of this white paper discusses chip-level design considerations that must be considered to achieve the lowest possible power consumption at the silicon device level. Download this white paper from Silicon Labs to learn how to develop higher performance and more energy efficient applications.



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Designing Low-Power Embedded Systems, Part 2
By mastering the relationship between active power consumption, standby power consumption and the duty cycle, you can develop higher performance and more energy-efficient embedded systems that stretch the limits of portable applications. Divided into two parts, the second part of this white paper explores software decisions that you must make to optimize the embedded system for the lowest possible power consumption. Download this white paper from Silicon Labs to learn how to develop higher performance and more energy efficient applications.



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Optimize Embedded Designs with a Flexible 32-bit USB MCU Architecture
MCUs provide versatile, configurable platforms for embedded systems, giving developers the flexibility to implement new system features easily and efficiently through firmware updates and I/O changes. However, even minor I/O changes can cause headaches for engineers performing PCB design, especially in cost- and space-constrained systems commonly encountered in MCU applications. Download this white paper from Silicon Labs to learn how to minimize design headaches with a highly flexible 32-bit microcontroller architecture.



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Top Considerations When Selecting a 32-bit ARM Microcontroller
Selecting the right 32-bit ARM microcontroller shouldn’t mean you have to compromise on your requirements. In addition to meeting your specific memory and I/O needs, it should also offer the integration, peripherals and power budget that gives you the most options and the best cost profile for your system. Download this white paper from Silicon Labs to learn about the latest innovations in 32-bit MCUs and get tips on how to select the best MCU for your design.



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Designing Power Efficient Gas and Water Utility Meters
Designing a smart water or gas utility meter can present a vexing low-power challenge for embedded control systems requiring RF connectivity. Since a single service call from a technician often exceeds the entire cost of the smart meter, battery life must exceed 20 years. Download this white paper from Silicon Labs to find out how to design power efficient meters.



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Top Design Considerations for Low-Power Metering Applications
As green energy management becomes a global imperative, the idea of implementing intelligent systems and wireless technology to more efficiently use energy and other natural resources has become a pervasive reality. It began with a relatively simple idea. If you add embedded intelligence and a communications link to a traditional metering device, you have the ability to remotely access the data that the smart meter has collected. However, through this seemingly simple enhancement of a communications link, a network was born, and with it came an explosion of applications and innovations transforming the way energy is measured, priced and consumed. Whether designing a new smart meter or equipment to retrofit existing meters, there are a number of design considerations that will result in power savings, wireless range improvement and lower system cost. Download this Silicon Labs’ white paper to learn more.



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Selecting the Optimal Battery
Engineers have many options when selecting the optimal battery to support and maximize service life of their next-generation portable or low-power applications. As batteries become more sophisticated in design and function, you must weigh a set of sometimes-conflicting requirements when determining the optimal battery type for your embedded system, including: energy capacity, terminal voltage, physical dimensions, self-discharge rate, power-delivery requirements, etc. Download this white paper from Silicon Labs to learn more about how to select the optimal battery for your embedded system.



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Low Power MCU Design for Portable Medical Devices
Engineers are under continuous pressure to push the envelope of cost, size, power consumption and performance in their next portable medical device designs. In order to be successful in the portable health care market products must above all be very reliable and accurate, but they must also be easy-to-use, low power, support a wide range of voltages, have easy and secure connectivity and of course low cost. Download this Silicon Labs’ white paper to learn how you can enable increased performance and reliability within strict power and cost budgets to address the stringent safety requirements and increasing competitive feature set in portable medical devices.



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Adding Class D Audio to Embedded Systems
Class D amplifiers can reach very high efficiency levels, resulting in significant power savings. However, the translation from the input signal to PWM and the PWM quantization itself can cause more distortion on the output than other amplifier architectures. The goal of a Class D amplifier implementation is to reduce this distortion to barely audible levels while maintaining very high power efficiency. This white paper from Silicon Labs discusses how to add utility Class D audio to 32-bit embedded systems in an unconventional way.



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Maximizing Wireless Network Range
The goal for wireless system manufacturers is to provide low-cost, robust nodes that maximize battery life while extending the range of the network as far as possible. Today’s developers have a wide range of RF technology choices when developing wireless networks and must consider many factors when selecting the best one for their design, including: sub-GHz versus 2.4 GHz frequency trends, operating range and battery life, sensitivity and data rate, and network topology and node intelligence. Download this white paper from Silicon Labs to learn more about what factors to consider in order to maximize range and battery life in low-cost wireless networks.



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Simplifying Humidity Measurement
Humidity sensing technology is critical to a wide range of applications, and despite its pervasive necessity and application across many industries, relative humidity measurement is among the more difficult technical challenges in environmental sensing. Download this white paper from Silicon Labs to review some of the basic principles of relative humidity measurement, and to learn how you can simplify humidity measurement with single-chip relative humidity and temperature sensor ICs.



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Using Constant Current Regulators in AC Applications
Constant Current Regulators (CCRs) simplify LED lighting circuit design while meeting requirements to keep the LED under a constant current condition, which is recommended for maximum LED efficiency (lumens per watt), color and lifetime. This application note includes information on 220V AC lighting circuits for LED with additional information on 120 V CCRs.



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Five Steps to Design a Compact, High-Efficiency PFC Stage
Learn to design a Discontinuous Conduction Mode PFC stage to optimize efficiency throughout load range and build in protection features for rugged operation—when cost-effectiveness, reliability, low stand-by power and high efficiency are critical. This paper summarizes the key steps for designing a PFC stage on a 160-watt, wide-mains evaluation board that can be easily applied to other applications.



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Simple Battery Charger using a CCR
Learn how Constant Current Regulators (CCRs) can be used in low-cost charging circuits for the three most common types of rechargeable batteries. The CCR provides a simple controller to terminate charging when Nickel Metal Hydride and Nickel Cadmium batteries reach the predetermined peak voltage of 1.5 V per cell. The CCR controller can also be used for recharging Lithium Ion batteries by eliminating trickle charges, which prolongs battery life by maintaining battery temperature in safe operating range.



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Enhanced, High-Efficiency Power Factor Controller
Learn how the new architecture in the NCP1612 PFC controller can help you extend the benefit of Critical Conduction Mode (CrM) PFC’s with enhanced light load efficiency and built-in protection features for improved reliability and safety without external components—when cost-effectiveness, reliability, and high efficiency are critical.



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High Efficiency 3A Buck Regulator With Light Load Efficiency
This design note features the flexible, synchronous NCP3170 high-efficiency buck regulator that accepts input voltages from 4.5 V to 18 V and drives 3 A loads at output voltages as low as 0.8 V.



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Speeding Up the Smart Grid
This white paper outlines a technique for delivering more robust, higher data rate communications for automatic meter reading.



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Power Supply and Power Adapter Solutions
Solutions guide to highly efficient power supplies featuring high active-mode efficiency, low standby-mode consumption and power factor correction.



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Smart Metering Solutions
This is a comprehensive guide to power management, protection and communications solutions for today’s smart metering applications.



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Minimizing energy consumption in capacitive sensing applications
Capacitive sensing is all about the ability to measure the capacitance, or more often the change in capacitance, between two or more electrodes. As a technique it is frequently employed to detect proximity or position but can also be used to measure humidity, fluid level and acceleration. Because capacitive sensing supports such a diverse range of applications, solutions are found in many different markets -­ from industrial, automotive and medical through to consumer.



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Testing Energy Efficient Designs
Energy efficient design techniques have created new and complex test challenges, requiring design engineers to make numerous difficult measurements and to troubleshoot fastchanging signals, complicated protocols, and small changes in voltage and current. As designs reach higher levels of energy efficiency, the right set of measurement tools can simplify and speed the often complicated tasks required for validating and debugging today’s evolving designs.




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Using Processors in the SOC Dataplane
Designers have long understood how to use a single processor for the control functions in an SOC design. However, there are a lot of dataintensive functions that conventional control processors (CPUs) cannot handle. That’s why designers have, for a long time now, designed RTL blocks for these challenging functions. However, RTL blocks take a long time to design and verify. Plus they are not programmable and thus not flexible enough to easily handle multiple standards or post-tapeout design changes.




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Optimize SOC Performance Using Memory Tuning and System Simulation
Memory tuning allows you to choose memory-related parameters for each on-chip processor core that balance system performance, processor area (cost), and memory size by exploring a target application’s sensitivity to these memory-system parameters. The processor core’s instruction-set simulator (ISS) plays a key and central role in this assessment because the ISS can model and report the expected system performance, providing a breakdown of memory-related stalls.




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How to Minimize Energy Consumption While Maximizing ASIC and SOC Performance
Power has become a first-order concern for ASIC and SOC designers right next to performance and area, whether the design is for portable mobile devices, for networking boxes, or for any other application. Optimizing a design for energy at an application and system level has the potential to cut processor and local-memory energy requirements by as much as half in many cases through intelligent design trade-offs. The amount of power savings made at the early architectural level far outweighs any potential power savings that might be made later at the RTL or physical design levels.




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How to Increase ASICs and SOC Computational Performance with Long-Word Processors
VLIW processors execute multiple independent instructions each clock cycle and provide a tremendous performance boost per clock cycle without incurring the exponential power-consumption increase caused by clock-rate increases. However, VLIW architectures have their own problems, particularly code bloat, which causes code footprints to balloon—thus increasing memory costs.




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Get Your ASIC Off the Bus
This white paper provides short descriptions of the most common hardware mechanisms—buses, direct connections, and data queues—used to interconnect processor cores on ASICs and SOCs. Except where explicitly noted, this paper assumes a one-to-one correspondence between tasks and processors. In fact, multiple tasks can be mapped onto one time-sliced processor and some tasks can be implemented by other non-programmable hardware accelerator blocks.




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Everything You Wanted to Know About SOC Memory (But Were Afraid to Ask)
This white paper discusses the many alternatives for on-chip and off-chip memory usage that SOC designers must understand to develop successful multicore SOCs. It discusses the essentials of SOC memory organizations for multicore designs, on-chip SRAM and DRAM, local memories and caches, on-chip non-volatile memories, and memory controllers for off-chip memory. It covers the difference between 6T and 4T SRAM designs, the system design ramifications of NAND and NOR Flash ROM, and how DDR2 and DDR3 SDRAMS compare (the differences might surprise you).




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Cut DSP Development Time – Get High Performance From C, No Assembly Required
Designers are asking their DSP cores to do more and more of the heavy workloads required for highly complex algorithms for filtering, FFT, MIMO, and other signal processing intensive applications. To get high performance from a conventional DSP core, developers have traditionally used assembly code programming, which is time consuming and difficult to maintain.




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Low Power Design and Verification Techniques
There are many techniques that have been developed over the past decade to address the continuously aggressive power reduction requirements of most ASIC and SoC designs. They include clock gating, multi-switching (multi-Vt) threshold transistors, multi-supply multi voltage (MSMV), power gating with or without state retention, dynamic voltage and frequency scaling (DVFS), and substrate biasing. The use of any of these techniques comes at a cost and their benefit varies depending on the technique used.




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Low-Power Physical Design with Olympus-SoC
Reducing power consumption has become a key design challenge at 45/32 nm technology nodes. For many designs, optimizing for power is as important as timing, due to the need to reduce package cost and extend battery life. However, the complexities of designing low-power chips can negatively impact performance and time to market. Designers are being forced to juggle macro-level functional complexity issues (multiple operational modes), and micro-level process and manufacturing issues (multiple design corners) that could have conflicting power, timing, signal integrity (SI), manufacturability, and area closure requirements.




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Top Design Considerations for Low-Power Metering Applications
As green energy management becomes a global imperative, the idea of implementing intelligent systems and wireless technology to more efficiently use energy and other natural resources has become a pervasive reality. It began with a relatively simple idea. If you add embedded intelligence and a communications link to a traditional metering device, you have the ability to remotely access the data that the “smart meter” has collected.




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How to Design Capacitive Touch & Proximity Sensing Technology into Your Application
What defines good human interface design, and how can system designers implement a smarter, friendlier and more intuitive solution? To begin answering these questions, it is helpful to view a human interface simply as a set of functional interactions with end users and their surroundings. These interactions can be subdivided into two logical groupings: inputs and outputs.




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Simplifying Power Supply Design in FPGA-based Systems
FPGA-based systems have become common and are appropriate for many applications. However, by their nature, FPGAs are power-hungry devices with complex power delivery requirements and multiple voltage rails. When FPGA power consumption increases, performance requirements on sensitive analog and mixed signal subsystems also increase, particularly on clocking subsystems that provide low jitter timing references for the FPGA and other board-level components. By using clock sources with integrated power supply noise rejection, designers can simplify power supply design and mitigate these design challenges.




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When to Use a Clock vs. an Oscillator
A wide range of timing solutions are available, including crystal oscillators (XO), voltage-controlled crystal oscillators (VCXO), and clocks. No one size fits all strategy applies when it comes to component selection. Picking the right device for a particular application is dependent on a number of factors, including whether or not the clocks must be synchronized to an externally provided reference clock, the system architecture of the processor and high speed serial data transmission ICs, and the frequency and jitter requirements of the end application.




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Enhancing Power Delivery System Designs with CMOS-Based Isolated Gate Drivers
As emerging green standards challenge designers to deliver more energy-efficient, cost-effective and reliable power delivery systems in smaller form factors, the need for greater power and isolation device integration becomes increasingly important. A critical building block within ac-dc and isolated dc-dc power supplies is the isolated gate driver.




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Low Power Design Basics
As the use of electronic devices pervades virtually every aspect of our lives, reducing power consumption must start at the semiconductor level. The power-saving techniques that are designed in at the chip level have a far-reaching impact. This is especially true with regard to the microcontrollers (MCUs) that serve as the intelligent engines behind a majority of today’s electronic devices.




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Developing Reliable Isolation Circuits
Over the last four decades, optocouplers have been the “default” signal isolation device, but recent breakthroughs in silicon isolation technology have spawned smaller, faster, and more reliable and cost-effective solutions that have already begun supplanting optocouplers in many end applications. This white paper discusses industrial isolation issues and ways RF isolation technology can be applied to increase system robustness and performance.



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