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2009 in Portable Design—the EDA Perspective

Walden C. Rhines, Chairman and CEO, Mentor Graphics

Portable design will continue to be a major driver of new EDA solutions in 2009, with an emphasis on increasing designer productivity, speeding time to market, and reducing power consumption. We’ll see improvements in four key areas: system- and architecture-level design exploration, power-aware functional verification, power-optimizing IC implementation, and rapid power-aware software development.

System-Level Power Design
Most system designers are still using spreadsheets for estimating power and making hardware-software partitioning decisions—an inaccurate and inefficient process. Next year we’ll see greater adoption of power-aware system-level design platforms that allow architectures to be tuned in the context of the overall target application. This dramatically expands the range of approaches that can be explored to minimize power and optimize the user experience with minimal impact to the design schedule. Some of the key exploration capabilities include:

  • Comparing data representation and processing choices, such as trading off hardware-intensive compression/decompression vs. data transmission volume, or deciding between general purpose processors and hardware accelerators.
  • Assessing the impact of sleep, power-down and various other modes on power, performance and user experience.
  • Maximizing cache, memory management, bus structure and bus arbitration schemes to eliminate bottlenecks and wasted power caused by contention and transfer delays.

High-level synthesis tools allow designers to describe algorithms in un-timed ANSI C++, enabling them to balance area, performance and power without resorting to hand-coded RTL. This gives designers the leverage they need to optimize individual blocks for performance and power by scaling clock frequencies, and using closed-loop power analysis for early power estimation. Bit-accurate data modeling allows numerical algorithm refinement to further reduce area and power.

Power-aware Functional Verification
Early verification improves productivity by identifying power and other design problems when it is easier and cheaper to resolve them. Functional verification of low power designs requires a power-aware simulator that understands design intent as captured in Unified Power Format (UPF), and works with a high-level language to express behavior and logical assertions that define system constraints. Using this information, the tool can model the logical integrity of the design, detecting data corruption that could result from power cycling. The tools can insert power-related functionality such as switches, isolation buffers, level shifters, and retention registers to prevent power-down errors. The tools also facilitate assertion debugging and provide a high level of design confidence through coverage-driven verification with automatic generation of coverage metrics and data. Finally, modeling and verification tools ensure accurate translation to RTL by automatically generating verified RTL from C++ descriptions, including clock gating and interfaces to system functions for dynamic clock and voltage scaling management.

Power-optimizing Implementation
At the IC implementation level, the latest tools support power-aware place-and-route for digital hardware logic. Advanced P&R tools insert clock and power gating circuitry and multiple voltage supply rails, correctly place and route blocks across multiple voltage domains, and route around voltage islands appropriately, inserting level shifters as needed. The layout of the clock tree structure can have a big impact on dynamic power, since clocking accounts for as much as 30% of total power consumption in an IC. Low power SoCs can have dozens of clock trees operating at different rates, times, and modes. During routing, clocks buffers are added to compensate for unequal path lengths, but these consume a significant amount of power. To reduce consumption, the layout must be optimized to meet spec with the minimum number of clock buffers. This is only possible if the P&R tool is able to concurrently analyze timing, power, and signal integrity across all design modes and corners as the routing is being done, a feature called multi-corner, multi-mode optimization.

Software Development and Power-aware Software
With software development, testing and integration taking an ever-larger proportion of development time and resources, tooling is this area is a prime concern for portable development. Portable designers now have a comprehensive choice of pre-built and optimized components including real-time operating system kernels, bus management, file system, database, security/encryption, USB, networking, and graphics services. We’ll see increasing use of Eclipse-based environments that support concurrent hardware and software development with simulators for hardware components such as Ethernet, Bluetooth, GSM/GPRS, serial, LCD, touch screen, keyboard, and storage media.

While the hardware enables power savings, the software controls it.  To ease power management chores, tools will increasingly be pre-integrated with popular IP such as ARM’s Intelligent Energy Management (IEM) facility. Power-aware embedded OS’s provide support for voltage and frequency scaling management, and profiling of system operations to set the appropriate power settings to get the job done. 

System Simulations predict system power use in operation. As multi-core processors grow in importance as a way to reduce power consumption, tools to reduce the difficulty of programming them and to simulate their real-time operation will also be in high demand.

Mentor Graphics Corporation
Wilsonville, OR
(503) 685-7000
www.mentor.com

This article first appeared in the January, 2009 issue of Portable Design. Reprinted with permission.

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