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SOI Industry Consortium publishes technical paper on porting semiconductor designs from bulk silicon to FD-SOI

Ability to Leverage Existing IC Designs Can Speed Time-to-Market for FD-SOI Devices at the 20nm Node

Boston, MA, November 11, 2011 – A group of leading semiconductor companies have developed a roadmap for leveraging CMOS designs intended for manufacturing on bulk silicon to fabricate ICs on fully depleted silicon-on-insulator (FD-SOI) substrates with ultra-thin buried oxide layers, producing chips with improved performance and lower operating power. The companies involved in this collaborative research effort – including SOI Industry Consortium members ARM, Leti, Université Catholique de Louvain (UCL), IBM, GlobalFoundries and Soitec – have published their findings in a new white paper titled “Considerations for Bulk CMOS to FD-SOI Design Porting.”

“This work shows that porting circuits from bulk silicon to FD-SOI can be very direct, depending on the FD-SOI technology used by a specific chipmaker,” said Horacio Mendez, executive director of the SOI Industry Consortium. “Design porting can enable shorter time-to-market for FD-SOI-based devices. Porting existing bulk CMOS designs to FD-SOI will lead to further optimization of ICs at the 20nm node and even faster implementation of FD-SOI devices.”

The research, which examined both bulk-to-FD-SOI IP porting and full-chip design porting, determined that using existing planar designs with minimal adjustments is especially viable for standard cell libraries, memory compilers and most I/Os, with slightly more efforts for some types of analog and mixed-signal designs.

In terms of circuit performance, the key benefits of using FD-SOI over planar bulk CMOS include:

  • Faster operation at equivalent leakage current, with FD-SOI’s advantage becoming even larger at lower supply voltages (Vdd)
  • Power savings of up to 40 percent, enabled by FD-SOI’s ability to reach the same operating frequencies as bulk CMOS at significantly lower supply voltage
  • Greatly reduced variability, with a positive impact on the minimum supply voltage of SRAM arrays, chip-level leakage, etc.
  • The ability to operate complete IP cores or full chips at very low supply voltages down to 0.5-0.6 volt
  • Excellent responsiveness to back-bias, a powerful option available in FD-SOI devices to boost performance, cut leakage power and reduce corner variations
  • Enhanced efficiency of other low-power design techniques such as DVFS (Dynamic Voltage and Frequency Scaling) etc.

The new white paper’s section on “Impact Per Design Domain” examines two paths for full-chip design porting. The most straightforward and fastest porting from bulk silicon to FD-SOI aims at not changing the place-and-route and modifying as little as possible the graphic database system (GDS) contents. The second approach optimizes the system-on-chip (SOC) design to take full advantage of FD-SOI enhancements such as back-biasing.

Appendices and reference sections in the white paper provide details on the various technology issues involved and links to FD-SOI technical papers presented at top industry conferences in recent years.

In addition to accommodating bulk-silicon designs, FD-SOI technology enables simplified processing of semiconductor devices, using fewer steps than fabricating ICs on bulk silicon. This streamlining means that, at upcoming technology nodes, it will cost less to manufacture semiconductors on FD-SOI wafers than on bulk silicon, as quantified in a recent study by IC Knowledge.

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